Microstrip

Choose a single trace or a symmetric differential pair, then its dielectric stack. Width is the width of each trace; pair spacing is measured edge to edge. Differential impedance is measured across +/−, and width synthesis holds the edge gap fixed.

Microstrip impedance depends on trace width $w$ relative to trace-to-ground separation $h$. With $u=w/h$, the Hammerstad–Jensen model relates the line impedance to the same geometry filled entirely with air:

Both impedances are in ohms. Effective relative permittivity $\epsilon_{\mathrm{eff}}$ accounts for the fields shared between air and substrate; the model derives it from geometry and substrate relative permittivity $\epsilon_r$.

Effective permittivity also slows propagation. At frequency $f$ in hertz, guided wavelength $\lambda_g$ in metres is:

Here $c$ is vacuum light speed. A line of length $\ell$ metres has delay $\tau=\ell\sqrt{\epsilon_{\mathrm{eff}}}/c$ seconds in this model. It excludes loss and frequency-dependent dispersion.

An exposed single trace retains the Hammerstad–Jensen model above. Covered traces and pairs use electrostatic capacitance per unit length, calculated once with the entered dielectrics and once with the same geometry filled with air:

The subscript identifies the single, odd or even mode. Capacitances are in farads per metre. Opposite voltages drive the odd mode; equal voltages drive the even mode. Differential impedance is twice the odd-mode impedance, and common-mode impedance is half the even-mode impedance. The main pair delay and wavelength use odd-mode effective permittivity. A closed-form fit and a numerical model can differ slightly at the bare limit.

Soldermask is a uniform planar cover above the trace plane. Embedded microstrip has a finite dielectric cover to air; it has one lower ground plane and is not stripline. Enter the cover thickness above the trace, not the total board thickness. The drawing shows the entered stack, with schematic proportions.

Bare single-trace limits are 0.01 ≤ w/h ≤ 100 and 1 ≤ substrate εᵣ < 128. The layered calculation supports 0.05 ≤ w/h ≤ 10, 1 ≤ each dielectric εᵣ ≤ 20, 0.02 ≤ gap/h ≤ 10 for pairs and 0 ≤ cover/h ≤ 20. Numerical refinement is checked; unresolved cases are unavailable. A small synthesis residual or refinement change does not establish fabrication accuracy.

All options assume zero copper thickness and a uniform, lossless, nondispersive stack. Finite copper, trapezoidal etching, conformal sidewall coating, material loss, roughness, radiation and pair asymmetry are excluded. Width sensitivity varies both pair widths equally while holding the edge gap, cover and dielectric values fixed. It is not a combined fabrication tolerance.

Generated values from direction or unit changes display at most two decimals while retaining full precision for calculations, sensitivity and copying until edited. Use the actual fabrication stackup for a final controlled-impedance design.