Impedance matching designer

A matching network transforms the load so its input impedance $Z_{\mathrm{in}}$ equals the real source/system resistance $Z_0$ at the design frequency $f_0$:

The target input impedance is a positive, real value in ohms, also used as the reference for input return loss and VSWR. Frequency is in hertz. L networks can match complex loads with positive resistance. π and T synthesis requires real positive terminal resistances. Their construction Q sets the network shape; component Q instead describes loss. Construction Q alone does not predict bandwidth.

A lossless quarter-wave line can match two real terminal resistances $R_1$ and $R_2$. At its design frequency, the required line impedance is their geometric mean:

Here $Z_t$ is the line’s characteristic impedance in ohms. This option assumes constant wave speed and real positive terminal resistances.

Calculated values, E12/E24 preferred values and finite-component-Q results are evaluated separately. Generated component inputs display at most two decimals while keeping full precision until edited. Editing a component evaluates the current physical circuit. Subsequent load, reference and frequency changes keep those edited parts; Recalculate match, a new circuit solution, topology or value series replaces them. The main input impedance, return loss and VSWR use ideal components with the selected values. The separately labelled Q-based power loss uses the same component Q for every part and includes mismatch as well as dissipation. Frequency sweeps hold the entered load and component Q fixed. Voltage and current estimates use ideal lossless parts and describe RMS stress, not peak ratings. Tolerance checks sample endpoints and do not guarantee the worst case between them. Verify real parts, parasitics, layout and the load at its intended reference plane. Compare power loss as well as reflection, because dissipation can improve the apparent match. Power loss includes mismatch; return-loss plots cap ideal matches at 60 dB, and the 10 dB guide is not a universal specification.

Differential mode connects a balanced input to a balanced load. Enter the complete load and positive real reference resistance across + and −, rather than a per-leg impedance. The differential voltage is the voltage between those conductors; differential current enters one leg and returns through the other:

Changing port type keeps the entered load/reference numbers and converts the current physical parts to preserve their equivalent circuit, without recalculating the match. 100 Ω is an optional differential reference preset. Each ± series field controls two equal, uncoupled components, one in each leg. Bridge components connect directly across the pair.

For the same full-port equivalent series element, each physical series inductor is half the equivalent inductance, while each physical series capacitor is twice the equivalent capacitance. Bridge values stay unchanged:

E12/E24 rounding is applied to those physical values before the circuit is evaluated. Available source power is the total differential-port power. At the nominal balanced values, each series component has half the equivalent pair voltage and the same current; bridge stress is across the pair. Tolerance samples vary every physical component independently and then evaluate the complete differential loop. They do not predict common-mode or balance performance. A balanced quarter-wave line uses full differential characteristic impedance; its displayed impedance is not a per-conductor value. Common-mode impedance, imbalance, mode conversion, mutual coupling and balun behaviour are outside this model.