RF Systems
Translate a product need into an RF architecture whose link, noise, linearity, waveform, clock, power, and verification budgets reconcile.
- Sequence
- 7 modules
- Available now
- Modules 05.1–05.7
- Prerequisites
- Paths 02–04
- Recurring case
- Node + gateway
Keep the need connected to the evidence.
For systems engineers, technical leads, component designers and validation engineers. Requirements flow into allocations; evidence and uncertainty return to the decision.
Module 05.1 develops measurable requirements, owned assumptions, margins and trace links with a printable conditional baseline.
Signals & Modulation, Transmission Lines & Matching, and RF Components & Circuits.
- Reconcile requirements with frequency, receive, transmit and converter budgets.
- Explain the binding constraint and its reference plane, mode and evidence.
- Compare architectures after screening hard constraints, then choose discriminating evidence.
Seven decisions. One system record.
All seven lessons are available, including the ungraded System architecture review. Availability does not certify whole-path completion or validate hardware.
- 01
From Product Need to RF Requirements
Turn ambiguous claims into conditional, traceable requirements and evidence requests.
Open module10 sections
- Failure: “100 m range” is not an RF requirement
- Define the use scenarios first
- Operational modes and worst credible combinations
- Write a complete requirement statement
- Balance link, throughput, energy, coexistence, size, cost, and markets
- Requirement, allocation, assumption, target, or result?
- Margin, reserve, guard band, and uncertainty are different
- Trace product claims to verification and back
- Rank uncertainty and retire risk early
- Baseline the node/gateway requirements table
- 02
Receiver Architectures & Frequency Planning
Compare conversion plans, images, aliases, and protected frequency regions.
Open module10 sections
- Failure: a clean block diagram hides a collision
- Architecture is a chain of spectral transformations
- Direct conversion: integration with DC and I/Q costs
- Low IF: move DC, inherit image rejection
- High IF and superheterodyne: separation for more stages
- RF sampling: alias zones do not remove the analog front end
- Injection side and orientation at every plane
- LO harmonics, clocks, digital emissions, and half-IF threats
- Compare filters, tuning, settling, calibration, cost, and power
- Create the gateway frequency plan
- 03
Sensitivity, Gain & Noise Budget
Reconcile weak-signal performance across bandwidth, gain, noise, and reference planes.
Open module10 sections
- Failure: three “-174 dBm/Hz” answers disagree
- Define sensitivity at a plane and quality threshold
- Noise bandwidth is not a generic channel width
- Source temperature and loss before the LNA
- Use Friis as an allocation
- Connect SNR, Eb/N0, bit rate, symbol rate, and coding
- Keep every margin in its own row
- Distribute gain without sacrificing dynamic range
- Check temperature, frequency, spread, and mode corners
- Reconcile the gateway sensitivity budget
- 04
Blockers, Linearity & Gain Control
Locate the first overloaded stage and allocate coexistence headroom.
Open module10 sections
- Failure: sensitivity passes, the nearby transmitter wins
- Catalogue every blocker and coupling path
- Propagate levels and compression headroom
- Intermodulation products and intercept approximations
- Cross-modulation, compression, and NF degradation
- LO phase noise causes reciprocal mixing
- Place filtering, linearity, and gain together
- AGC needs states, thresholds, hysteresis, and time
- Protect converter full scale and digital headroom
- Build wanted-plus-blocker operating corners
- 05
Transmit Power, Fidelity & Efficiency
Balance conducted power, waveform quality, duty cycle, and energy.
Open module10 sections
- Failure: more PA power makes the product worse
- Conducted, accepted, and radiated power use different planes
- Build the transmitter gain and loss lineup
- Waveform PAPR sets PA backoff
- Allocate EVM across the transmitter
- Track occupied bandwidth, regrowth, harmonics, and spurs
- Burst ramp, settling, and transient chirp matter
- Power control needs sensing and compensation
- Duty, heat, current peaks, supply droop, and coexistence
- Baseline the node transmit modes
- 06
Converters, Clocks & the Digital Boundary
Allocate full scale, sample rate, clock quality, and interface constraints.
Open module10 sections
- Failure: high bit count, low system performance
- Translate the analog distribution to converter input
- Full scale, dBFS, crest factor, and clipping margin
- SNR, SINAD, ENOB, SFDR, and noise density
- Sample rate, alias plan, and analog filters
- Aperture jitter creates a frequency-dependent ceiling
- Driver settling, common mode, kickback, and input network
- DAC images, zero-order hold, and reconstruction
- Word length, scaling, overflow, data rate, and latency
- Choose the gateway conversion and clock boundary
- 07
System Trade Study & Architecture Review
Screen hard constraints, compare evidence, and defend an architecture.
Open module10 sections
- Failure: the highest score violates a must-pass requirement
- Freeze scenario, assumptions, candidates, and common basis
- Screen hard constraints before scoring preferences
- Define independent criteria and value functions
- Assign weights with rationale and ownership
- Separate evidence maturity from performance
- Test sensitivity to weights and uncertain inputs
- Reconcile every RF interface and budget
- Retire risk with a discriminating experiment
- Conduct and record the architecture review