CPW & CPWG
Find width or impedance for a coplanar trace, with optional grounded backing.
CPW / CPWG geometry
Top trace plane to the substrate’s lower surface. Units apply to all geometry dimensions.
Measured edge to edge; this slot stays fixed when solving width.
Use the material value, not effective permittivity.
Calculated trace width w
1.87 mm
- Calculated impedance
- 50 Ω
- Effective relative permittivity
- 2.53
Cross-section schematic; proportions are illustrative. s is the slot on each side of the signal trace.
Side grounds, air above and below the substrate; no back ground. Zero-thickness, lossless estimate.
More measurements
Electrical length & phase delay
- Electrical length
- 140.29 °
- One-way phase delay
- 159.05 ps
- Guided wavelength
- 76.99 mm
Frequency changes propagation readings, not the quasi-static impedance. Phase delay equals group delay only in this nondispersive model.
Width sensitivity
Only width varies; height and each side slot and material stay fixed. This is not a combined fabrication tolerance.
| Trace | Width (mm) | Z₀ (Ω) |
|---|---|---|
| Narrower | 1.78 | 50.55 |
| Nominal | 1.87 | 50 |
| Wider | 1.97 | 49.49 |
Model range & numerical check
Calculation range: 1 ≤ εr ≤ 20; 0.01 ≤ w/h ≤ 10; 0.01 ≤ s/h ≤ 10. These are supported calculation bounds, not manufacturing limits.
Attainable impedance over supported widths: 35.68 Ω to 171.13 Ω.
- Width / height
- 1.17
- Velocity factor
- 0.63
- Forward residual
- 0 Ω
A small residual confirms numerical consistency, not manufacturing accuracy.
Model & assumptions
The signal runs between two side grounds. CPW has air beneath the substrate; CPWG adds a continuous back ground. All ground conductors are assumed to share one reference potential. Width synthesis holds each side slot fixed.
Let R(k) be the complete elliptic-integral ratio K(k)/K(k′), with k′ = √(1−k²). The moduli describe the unbacked and grounded substrate boundaries:
For CPW, the dielectric filling and impedance are:
Adding the ideal back ground changes both filling and impedance:
These are quasi-static partial-capacitance estimates. The implementation evaluates K using arithmetic–geometric means, with η₀ =376.730313668 Ω. Copper thickness, soldermask, finite grounds, via fences, slotline modes, losses and dispersion are excluded. Ground bonding must be designed separately. Supported calculation bounds are 0.01≤w/h≤10, 0.01≤s/h≤10 and 1≤εᵣ≤20; they are not accuracy guarantees.
Both tools derive propagation from the selected effective permittivity. Frequency and length affect these readings independently of impedance:
Here c=299,792,458 m/s. Phase delay equals group delay only within this nondispersive model.
Independent example: w=1 mm, each slot s=0.2 mm, h=1 mm and εr=4.3 give 58.74 Ω for CPW or 51.74 Ω for CPWG. Numerical residuals are not fabrication tolerances.
Does a result look wrong? Report a calculation issue
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