Sampling & Digital Representation

01 / 10

A clean digital tone at the wrong analog frequency

A record shows a clean 0.7 MHz cosine. Did the converter input contain 0.7 MHz?

Think about itAt 5 MS/s, name at least three nonnegative analog frequencies that produce that real sampled cosine.

Answer

0.7, 4.3, 5.7, 9.3, 10.7, and 14.3 MHz are all candidates. In general, kfs ± 0.7 MHz has the same sample values, with cosine symmetry removing the sign distinction. Only the analog path and pre-sampling filter tell us which candidate was admitted.

Ambiguity is not corruption. Sampling retained one equivalence class; the analog front end must select its intended member.

Recurring case · input plane A1 to sample plane D3/A0

A 10.7 MHz IF can legitimately become a 0.7 MHz digital IF

With fs = 5 MS/s, cos(2π · 10.7 MHz · n/fs) equals cos(2π · 0.7 MHz · n/fs). The samples are internally consistent. The unsafe step is claiming the analog input from the record alone.

EvidenceImpulse-sampling periodicity from Oppenheim et al. and Analog Devices MT-002; the listed frequencies are an internal direct substitution.

02 / 10

Sampling creates periodic spectral replicas

What mathematical operation makes the analog spectrum repeat?

Ideal uniform sampling multiplies the continuous waveform by an impulse train. Multiplication in time becomes convolution in frequency, so shifted copies of X(f) appear every fs.

$x_{s}(t) = x(t) \sum _{n} \delta (t - n T_{s})$ Ideal point sampling with T_s = 1/f_s.

$X_{s}(f) = T_{s}^{-1} \sum _{k} X(f - k f_{s})$ The scale factor depends on the transform convention; the support-overlap conclusion does not.

The preservation test is support separation after the declared filtering and representation. A sample-and-hold aperture response and code quantization are later, distinct operations.

Go deeperWhy this diagram is a support argument, not a converter response

The impulses are an ideal model. A physical track-and-hold has aperture behavior and a hold response; an ADC also adds noise, distortion, and finite codes. Those effects can attenuate or degrade a replica, but they do not repeal the alias equivalence created by uniform sampling.

EvidenceOppenheim, Willsky, and Nawab, Chapters 3–7; MIT OpenCourseWare Signals and Systems; Analog Devices MT-002.

03 / 10

Nyquist is about occupied support

Which frequency edge must a low-pass sample-rate claim protect?

For a signal whose entire analog support lies between 0 and B_max, a familiar sufficient ideal condition is strict separation of the positive and negative copies:

$f_{s} > 2B_{\mathrm{max}}$ Low-pass sufficient case, not a universal “twice something” slogan.

Common misconceptionSampling above twice the signal bandwidth always works, regardless of band position.

A 200 kHz-wide band at 10.7 MHz is not described by Bmax = 100 kHz in the low-pass theorem. Bandpass sampling can use a lower rate only when every zone placement, orientation, blocker, converter bandwidth, and analog filter obligation is checked together.

MathematicsExact bandlimitOccupied support ends at a declared edge.
HardwareFinite transitionReal filters need distance to accumulate rejection.
AllocationStrict marginTouching support at fs/2 leaves zero transition width.

Equality can be a mathematical boundary, but it is not a robust product allocation. A wanted edge at fs/2 and an unwanted edge immediately beyond it ask a realizable filter to change from passband to stopband with no frequency interval in which to do so.

EvidenceSampling theorem treatment in Oppenheim et al.; baseband and undersampling constraints in Analog Devices MT-002.

04 / 10

Real versus complex sampling

Does “80 ksample/s complex” mean 80,000 or 160,000 scalar values each second?

A real sequence has conjugate-symmetric spectral information: its negative-frequency half is constrained by its positive-frequency half. An ideal complex sequence carries independent I and Q coordinates and can represent a signed interval from −fs/2 to +fs/2 without that same redundancy.

Real · 80 ksample/s80k real values/sUnique ideal support: 0 to 40 kHz.

Complex · 80 ksample/s80k I + 80k Q values/sSigned ideal support: −40 to +40 kHz.

12 bits per scalar0.96 vs 1.92 Mbit/sBefore framing, line coding, or metadata.

Common misconceptionComplex sampling simply doubles bandwidth.

It changes the represented degrees of freedom and the meaning of one sample. State whether the rate counts complex pairs or scalar converter outputs. Then state whether I and Q come from two ADC paths, a digital downconverter, or another architecture; the word “complex” alone does not choose the hardware.

Think about itCan a ±6.75 kHz complex baseband fit ideally at 80 ksample/s?

Answer

Yes. Its 13.5 kHz total support fits inside −40 to +40 kHz, leaving 33.25 kHz on each side before the next periodic copy. That is an ideal digital-support statement; the analog I/Q filters or preceding rate-change filters still need explicit requirements.

EvidenceComplex-representation and signal-space conventions from Oppenheim et al. and Proakis & Salehi; arithmetic shown directly.

05 / 10

Bandpass sampling and alias-zone bookkeeping

Where do a wanted IF and two nearby blockers land after a 5 MS/s real sampler?

Divide the nonnegative analog axis into half-rate zones. Odd-numbered zones preserve frequency order; even-numbered zones reverse it under this counting convention. Fold every interval—not just its center.

Zone 10.0–2.5 MHzpreserved →

Zone 22.5–5.0 MHz← reversed

Zone 35.0–7.5 MHzpreserved →

Zone 47.5–10.0 MHz← reversed

Zone 510.0–12.5 MHzpreserved →

Zone 612.5–15.0 MHz← reversed

Checked 5 MS/s real-sampling case
A1 analog support	Zone	A0 support	Orientation	Disposition
9.2–9.4 MHz blocker	4	0.6–0.8 MHz	Reversed	Collides
10.6–10.8 MHz wanted	5	0.6–0.8 MHz	Preserved	Wanted
14.2–14.4 MHz blocker	6	0.6–0.8 MHz	Reversed	Collides

Because three analog supports become the same sampled support, no downstream DSP can separate them. The converter must also have specified analog input performance at 10.7 MHz even though the selected digital IF is only 0.7 MHz.

Go deeperEndpoint folding and orientation

The wanted edges satisfy |10.6 − 2(5)| = 0.6 MHz and |10.8 − 2(5)| = 0.8 MHz. For 9.2–9.4 MHz, the low analog edge maps to the high digital edge; the order reverses. Endpoint checks also expose a band that crosses a folding boundary and could overlap itself.

EvidenceNyquist-zone and undersampling treatment in Analog Devices MT-002; terminology context from IEEE 1241-2023; numeric fixture independently tested.

06 / 10

The anti-alias filter is part of the sampling plan

What must the analog filter do before the first sample makes unwanted energy inseparable?

01 · PassWanted support10.6–10.8 MHz at the ADC input plane.
02 · TransitionNearest threat1.2 MHz to either listed blocker edge.
03 · RejectAllocated stopbandDerived from blocker, noise, and margin—not a generic number.
04 · VerifyConverter planeInput bandwidth, noise, distortion, and clock conditions.

Passband10.6–10.8 MHzRipple and phase limits still open.

First listed stopband edge9.4 or 14.2 MHzRequired attenuation needs a system allocation.

Common misconceptionA brick-wall filter drawn at the Nyquist edge completes the sample plan.

A buildable requirement needs passband limits, a nonzero transition, stopband edges, rejection versus frequency, impedances and reference plane, and tolerances. For the default illustrative levels, 54 dB merely places a −20 dBFS colliding blocker below the selected −74 dBFS ideal floor; it is not a complete noise, linearity, or margin allocation.

A DAC reconstruction filter serves the opposite boundary: it suppresses images and hold-response consequences after samples are converted back to analog. It is not the ADC anti-alias filter in another location.

Handoff. Filter realization belongs in Path 04 module 04.3; converter and clock budgets belong in Path 05 modules 05.2 and 05.6. This lesson owns the requirements crossing those boundaries.

EvidenceAnalog Devices MT-002 distinguishes baseband/undersampling constraints and ADC anti-alias versus DAC image filtering; IEEE 1241-2023 supplies converter terminology.

07 / 10

Quantization, clipping, and dBFS

What does “12 bit” predict only after the code and full-scale conventions are declared?

For the checked bipolar convention, the ADC span is 2 Vpp, from −1 V to +1 V. An ideal N-bit uniform quantizer divides that span into 2^N steps. With rounding, the ideal error lies in ±q/2.

$q = \frac{2 V}{2^{12}} = 488.281 \mathrm{\mu V}$ $e_{\mathrm{rms}} = \frac{q}{\sqrt{12}} = 140.955 \mathrm{\mu V} \mathrm{RMS}$ $V_{\mathrm{sine,rms}} = \frac{1}{\sqrt{2}} V = 0.707107 V \mathrm{RMS}$

$\mathrm{SNR}_{\mathrm{ideal,FS sine}} \approx 6.02N + 1.76 = 74.00 \mathrm{dB}$ Coefficient-rounded textbook form, noise integrated over DC to fs/2.

Code convention: Ideal uniform rounding; 4096 steps across 2 Vpp.
Amplitude convention: 0 dBFS is the full-scale sine peak; −6 dBFS lowers its ideal quantization SNR to 68.00 dB.
Clipping rule: A peak above 0 dBFS is rejected; a quantization-SNR number is suppressed.
What 74 dB omits: DNL/INL, thermal noise, distortion, jitter, aperture response, reference noise, and implementation margin.

The q/√12 and 6.02N + 1.76 results require the ideal uniform-error model and a sufficiently busy signal. They change with input backoff and measurement bandwidth. A real converter’s SINAD, ENOB, and SFDR must come from stated operating conditions, not from nominal bits alone.

Checked valuesServer model: q = 488.281 µV; noise = 140.955 µV RMS; full-scale sine = 0.707107 V RMS. Source derivation: Analog Devices MT-001.

08 / 10

Quantization error is not always white noise

Can two records have similar quantization-error RMS but very different spectra?

Yes. A coherent, low-level periodic input can make the error repeat with the waveform, concentrating it into discrete spectral lines. A signal that traverses many code phases—or enough added noise—can decorrelate the error so a noise-like model is more useful. The same RMS total does not imply the same spectral consequence.

Coherent low-level inputPeriodic error patternMay appear as harmonics or spurs; the white-noise picture can fail.

Sufficiently varying inputDecorrelated errorq/√12 and an approximately flat distribution can become useful assumptions.

Intentional ditherTrade spurs for noiseCan decorrelate error, but raises the noise floor; implementation is deferred.

Common misconceptionEach added bit guarantees 6.02 dB more measured system SNR.

The slope belongs to the ideal full-scale sine quantization model. Analog noise, distortion, clock error, input amplitude, bandwidth, and correlated quantization can bind first. Nominal bits, ENOB, SINAD, SFDR, and noise density answer different questions and cannot be substituted without their definitions.

Go deeperWhy bandwidth changes an in-band quantization-noise claim

The textbook 6.02N + 1.76 value integrates the ideal error across the full Nyquist band. If subsequent filtering keeps a smaller band and the error is reasonably white, in-band noise falls. That processing gain must state its bandwidth and must not be applied to coherent spurs as though they were white noise.

EvidenceAnalog Devices MT-001 explicitly states the q/√12 assumptions and correlation caveat; IEEE 1241-2023 is used only for ADC test vocabulary.

09 / 10

Clock frequency error and aperture jitter differ

Why does 1 ps look generous at 10.7 MHz and severe at 2.45 GHz?

A static sample-rate error changes the mapping between sample index and time, so estimated frequency and timing scale are wrong. Random sample-time variation instead evaluates the waveform at a slightly wrong instant. For a sine and small RMS timing uncertainty, amplitude error grows with the analog input slope.

$\mathrm{SNR}_{j} = -20 \log _{10}(2\pi f_{\mathrm{in}}\sigma _{t})$ Sinusoidal, small-error, RMS bound; fin is analog input frequency, not occupied bandwidth.

10.7 MHz · 1 ps RMS83.45 dBIdeal sinusoidal jitter ceiling.

2.45 GHz · 1 ps RMS36.25 dBSame time error, much steeper analog sine.

Double fin−6.0206 dBDirect logarithmic consequence.

Use total RMS timing uncertainty only after stating which independent contributions are combined. Clock phase noise and deterministic spurs require more detailed spectral treatment; the scalar formula is an orientation bound, not a complete clock budget or an ADC guarantee.

Interactive · alias-quantization/1.0 · deterministic ideal-bound model

Alias & Quantization Planner

Declare the analog support, sampling representation, interferers, full-scale convention, and clock uncertainty. The planner either defends the ideal geometry or names the first reason to reject it.

Sampling representation

Real samplesComplex I/Q

Wanted centerOccupied total widthSample rate

Candidate analog blockers · up to four

UseLower blockerCenter · MHzWidth · kHzLevel · dBFS

UseUpper blockerCenter · MHzWidth · kHzLevel · dBFS

UseBlocker 3Center · MHzWidth · kHzLevel · dBFS

UseBlocker 4Center · MHzWidth · kHzLevel · dBFS

Full-scale convention

Bipolar VppNormalized ±1

Full-scale spanWanted sine peakNominal resolutionRMS timing uncertaintyAnalog input for jitter

Planner decisionReject this plan

Alias geometry binds first: Lower blocker and Upper blocker maps into or touches the wanted digital interval, so digital processing cannot separate it afterward.

Wanted fold in A0: 600.000 kHz to 800.000 kHz · zone 5 · preserved
Nearest digital alias gap: 0.000e+0 Hz
Nearest A1 transition: 1.200 MHz
Clipping margin: 6.00 dB
Lower selected ideal ceiling: 68.00 dB

Wanted support · solid hatch
Blocker support · dashed hatch
Three adjacent sample periods are shown; overlap is geometry, not attenuation.

Interval-collision check

Lower blocker: overlap with the wanted support at 600.000 kHz to 800.000 kHz.
Upper blocker: overlap with the wanted support at 600.000 kHz to 800.000 kHz.

Folded intervals and orientation
Source	Analog A1 support	Zone	Digital A0 support	Orientation	Relation
Wanted band	10.600 MHz to 10.800 MHz	5	600.000 kHz to 800.000 kHz	preserved	2 listed collisions
Lower blocker	9.200 MHz to 9.400 MHz	4	600.000 kHz to 800.000 kHz	reversed	overlap
Upper blocker	14.200 MHz to 14.400 MHz	6	600.000 kHz to 800.000 kHz	reversed	overlap

Ideal bound ledger

q: 488.281 µV
Quantization noise RMS: 140.955 µV
Full-scale sine RMS: 707.107 mV
Full-scale sine SNR: 74.00 dB
Amplitude-adjusted SNR: 68.00 dB
Sinusoidal jitter ceiling: 83.45 dB
Scalar values / second: 5.000 Mvalue/s
Uncoded sample payload: 60.000 Mbit/s

Analog obligation

54.00 dB

At least 54.00 dB would place the strongest listed colliding blocker below the selected ideal ceiling. This is not a complete system rejection allocation.

Transition width, passband ripple, stopband edge, converter noise/distortion, and implementation margin remain system requirements.

Reference plan decisions
Candidate	Decision	Reason or obligation
5 MS/s real, wanted 10.6–10.8 MHz, listed 9.2–9.4 and 14.2–14.4 MHz blockers	Reject	All three supports fold onto 0.6–0.8 MHz; the blockers are inseparable after sampling.
Wanted support exactly touches a folding boundary	Reject	Equality leaves zero transition allocation. “fs = 2B” is not a realizable anti-alias filter specification.
80 ksample/s complex baseband, ±6.75 kHz wanted support	Defend conditionally	Periodic replicas are ideally separated. Specify an analog I/Q or digital-downconversion architecture and reject out-of-band energy before the rate change.

Model boundary. Support intervals have hard edges; folding uses a documented tolerance of max(1 µHz, fs × 10⁻¹²). The model is ideal and deterministic. It does not model filter shape, aperture response, DNL/INL, thermal noise, harmonic distortion, clock spectra, metastability, or regulatory masks.

JavaScript is unavailable, so controls cannot update. The server-rendered checked case remains complete: a 10.6–10.8 MHz wanted band sampled real at 5 MS/s folds to 0.6–0.8 MHz in zone 5 with preserved orientation. Both 9.2–9.4 and 14.2–14.4 MHz blockers fold onto the same interval with reversed orientation, so the plan is rejected. For 12 bits and 2 Vpp, q = 488.281 µV, ideal quantization noise RMS = 140.955 µV, full-scale sine RMS = 0.707107 V, and the coefficient-rounded full-scale ideal SNR is 74.00 dB. At −6 dBFS the amplitude-adjusted ideal quantization ceiling is 68.00 dB; 1 ps RMS at 10.7 MHz gives 83.45 dB, so quantization is lower among those two ideal bounds. The nearest listed analog transition is 1.2 MHz and the illustrative rejection-to-ideal-floor check is 54.00 dB, not a complete system allocation.

Reject. Wanted band folds to 600.000 kHz to 800.000 kHz · zone 5 · preserved. Alias geometry binds first: Lower blocker and Upper blocker maps into or touches the wanted digital interval, so digital processing cannot separate it afterward.

EvidenceAnalog Devices MT-007 and MT-031 for sinusoidal aperture-jitter orientation; checked numeric fixtures are independently evaluated in the lesson model tests.

10 / 10

Update the sample plan

Which proposal survives when representation, support, filtering, headroom, and timing travel together?

Defend conditionally · canonical D3/A0

80 ksample/s complex baseband

10 ksymbol/s QPSK candidate, α = 0.35, occupied support ±6.75 kHz, 8 complex samples/symbol.

Ideal periodic copies are separated.
Rate means 80k I plus 80k Q scalar values/s.
Analog I/Q ADCs or the preceding digital downconverter and filters remain architecture requirements.

Reject · alias collision

Unfiltered 10.7 MHz real IF

5 MS/s, 200 kHz wanted support, with listed bands at 9.3 and 14.3 MHz.

All supports map onto 0.6–0.8 MHz.
Post-sampling separation is impossible.
A system-derived analog rejection requirement is mandatory.

Reject · no transition

Wanted edge exactly at fs/2

The ideal support merely touches the first periodic copy.

Zero analog transition width.
Component tolerance and drift have no allocation.
Increase fs, narrow support, or move the band.

Plane and representation: D3/A0 complex baseband is canonical; A1 real IF is a conditional variant.
Support: Canonical ±6.75 kHz; IF wanted 10.6–10.8 MHz.
Sample-rate accounting: 80 ksample/s complex = 160k scalar values/s. IF variant = 5M real values/s.
Scaling/headroom: 2 Vpp bipolar example; wanted peak −6 dBFS; clipping forbidden.
Selected ideal ceilings: 12-bit example: 68.00 dB at −6 dBFS; 1 ps at 10.7 MHz: 83.45 dB.
Unknown ledger: Analog filter response, ADC SINAD/SFDR, driver, aperture behavior, clock spectrum, tolerances, and margin.

Decision

Carry the complex-baseband plan forward as the canonical waveform record. Keep the real-IF plan only as an implementation variant after an analog filter and converter budget demonstrate that the colliding bands are suppressed. Do not accept an equality-edge plan.

Artifact boundary. This record preserves a declared sample support. It does not yet define the bit-to-symbol mapping, normalization, decision regions, or receiver error rule.

Ungraded review

Check your understanding

Answer each question in your own words, then reveal the model answer.

01Why can one real sampled tone correspond to several analog frequencies?
Model answer
Uniform sampling makes shifted spectral copies periodic in fs. For a real sinusoid, conjugate symmetry also removes the sign distinction, so frequencies related by kfs ± f produce the same discrete-time cosine unless analog filtering supplies more information.
02Why is ‘sample at more than twice the occupied bandwidth’ incomplete?
Model answer
Bandwidth alone does not locate the support. A sampling plan must account for every wanted and unwanted interval after folding, the real or complex representation, converter input bandwidth, and achievable analog rejection before sampling.
03Fold 10.6–10.8 MHz through a 5 MS/s real sampler.
Model answer
Both edges are 10 MHz plus 0.6 or 0.8 MHz, so the interval appears at 0.6–0.8 MHz. It lies in half-rate zone 5 and keeps its orientation. Bands at 9.2–9.4 and 14.2–14.4 MHz reverse into the same output interval.
04For an ideal 12-bit, 2 Vpp bipolar quantizer, what are q and the full-scale sine SNR?
Model answer
q = 2/4096 V = 488.281 µV. Under the uniform uncorrelated-error model, q/√12 = 140.955 µV RMS. The coefficient-rounded full-scale sine result is 6.02(12)+1.76 = 74.00 dB over the full Nyquist band.
05How does sample-rate error differ from random aperture jitter?
Model answer
A static rate error changes the time and frequency scale. Random timing uncertainty converts a waveform's local slope into amplitude error; for a sine its ideal small-error ceiling depends on analog input frequency through −20 log10(2πfinσt).
06What belongs in the analog-filter boundary of a sample plan?
Model answer
State the converter input plane, wanted passband, nearest folding threats, transition width, required stopband rejection derived from a blocker/noise allocation, passband limits, converter analog bandwidth, and unresolved margin. A brick-wall sketch is not a build specification.

Sources and model provenance

Sources were checked during implementation. Equations and numeric fixtures are reproduced as short internal derivations; linked sources establish the underlying models and terminology, not a product guarantee.

Primary references

A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems, 2nd ed., 1996, Chapters 3–7.
J. G. Proakis and M. Salehi, Digital Communications, 5th ed., 2008, Chapters 2, 4, and 5.
MIT OpenCourseWare · Unified Engineering Signals and Systems, open instructional cross-check.
IEEE 1241-2023, active standard published 2023-10-06; ADC terminology and test-method vocabulary.

Converter and sampling tutorials

Analog Devices MT-002, Nyquist zones, baseband and undersampling constraints, and filter boundaries.
Analog Devices MT-001, Rev. A (2008), ideal quantization step/noise/SNR and correlation caveat.
Analog Devices MT-007, Rev. A (2008), aperture jitter and analog-signal slope.
Analog Devices MT-031, Rev. A (2008), total clock-jitter orientation.

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02.5

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