RF Journey

01 / 10

Failure: high bit count, low system performance

The ADC has twelve bits. Why does the weak gateway signal have neither 74 dB SNR nor twelve effective bits?

Continue the fictional gateway from 05.2’s frequency plan, 05.3’s gain/noise budget and 05.4’s blocker corners. Its 2.450 GHz signal is translated to 100 MHz. The ADC samples that analog waveform 80 million times per second. The selected telemetry channel occupies only 13.5 kHz; the detector integrates noise over 20 kHz. None of those numbers is interchangeable.

Twelve nominal bits describe 4096 code bins. They say little about the driver’s settling, allowable input swing, common mode, clock uncertainty or largest unwanted spur. The weak wanted signal uses a small part of the full-scale voltage. Increasing bits can lower an ideal quantization floor while leaving analog noise, clipping or timing error as the binding limit.

Think about itKeep 1 ps total timing error and the same 80 MS/s clock. Does moving the analog input from 100 MHz to 2.45 GHz preserve the jitter ceiling?

Answer

No. The analog slope grows with input frequency. The sine jitter-only ceiling drops from 64.036402633 dB to 36.253080946 dB. The RF tone’s sampled alias is only 30 MHz, but using that alias in the timing formula would discard the physical slope that created the error.

Opening failure ledger · illustrative mechanisms, not measured failures
Attractive claim	Condition it misses	System consequence
More nominal bits	Wanted amplitude far below the named full-scale reference	Weak wanted-to-quantization ratio differs from full-scale sine SNR.
Higher sample rate	Analog input bandwidth, admitted alias images and timing quality	A faster interface can carry a corrupted signal.
Large SFDR	Spur reference, frequency and exact test condition	A discrete product may still land on the wanted channel.
Enough differential swing	Individual pin voltage and common mode	The driver or input buffer can leave its valid operating region.
AGC / digital filtering	Where compression or alias superposition first occurred	Processing after A0 cannot restore lost analog information.

Common misconceptionN bits means N-bit accuracy or N-bit ENOB.

Resolution, static accuracy and effective sine performance answer different questions. The production decision needs a set of compatible conditions. A code count is just one entry.

The first task is to move the existing analog ledger to the converter pins, with its reference and ownership intact.

02 / 10

Translate the analog distribution to converter input

Which quantities actually arrive at the ADC input, and which exist only after digital processing?

Illustrative low-IF receive path. Analog frequency, occupied support, noise bandwidth, ADC rate and downstream complex rate are different quantities.

A1 · analog inputDifferential volts, teaching dBm, common mode, driver, filters and admitted blockers.
A0 · physical code streamFull-scale reference, raw word, sample clock, alias orientation and transport.
D3 · selected complex streamI+jQ; translation and conjugation when required, valid filtering, scaling and decimation.
R3 · detectorQuality after the complete receive chain. A sine benchmark is not packet performance.

Frozen low-IF boundary · p05-m06-converter-boundary-v1; illustrative high-gain state
Quantity / plane	Exact input	Meaning / ownership
RF carrier / R0	2.450 GHz	Carrier before frequency conversion; no regional authorization implied.
Analog center / A1	100.000 MHz	Physical input frequency used for jitter.
Wanted support / A1	99.993250…100.006750 MHz	13.500 kHz total null-to-null support, inherited α=.35, 10 ksymbol/s waveform.
Noise integration / A1 → R3	20.000 kHz ENBW	Receiver-noise and added-ADC-noise comparison band; not signal support.
Wanted average / A1	−62.500000000 dBm	05.3 high-gain chain: −105 dBm at R2 plus 42.5 dB gain.
Receiver noise / A1	−85.665007875 dBm	Integrated over 20 kHz; RX-FE, RX-LNA, RX-MIX and RX-DRV already included.
Converter / A0	One real ADC, 80.000 MS/s, 12 nominal bits	16 bits transported per sample; external timing .8 ps and aperture .6 ps, independently supplied.
After channel selection / D3	80.000 kcomplex-sample/s	I+jQ, 16-bit I and 16-bit Q in the transport exercise; requires filtering before decimation.

Changing receive gain moves both wanted and downstream analog noise. Recalculate the upstream cascade when the gain distribution changes; do not translate only the wanted row. The 05.3 driver-28 variant has a different gain/noise balance, and 05.4’s AGC corners have different admitted blockers. The baseline here keeps the high-gain chain and blockers off.

Changing architecture also changes the analog-noise provenance. The RF presets retain the nominal level fields for comparison but withhold the inherited analog-noise total until a new A1 allocation is supplied. Their quantization and jitter-only screens can still be inspected independently.

Contributor ownership · avoid paying for the same impairment twice
Source ID	Included	Excluded / required handoff
RX-A1 / 05.3	Upstream thermal/device noise including RX-DRV at A1, 20 kHz	ADC, clock timing and deterministic spur errors excluded.
ADC-Q / ideal mode	Ideal independent white quantization only	No supplied SINAD, aperture, nonlinear distortion or new driver.
Synthetic sine row / specified mode	ADC noise plus distortion and test timing under the pinned test	No extra ideal quantization or included jitter addition; no weak-signal narrowband total.
ADC-EXTRA / disjoint exercise	Explicit new ADC additive-noise contribution	Replaces ADC-Q; must name same band/reference and exclusions.
DRV-NEW / optional	Only a genuinely added stage with disjoint provenance	Disabled by default. Reusing RX-DRV is a double count.
CLOCK / sine exercise	Independent total timing uncertainty	No in-band allocation without the error spectrum and receive transfer function.

Common misconceptionAn ADC driver is noiseless, or its noise should always be added to the receiver budget again.

The driver is a real contributor. Here it already belongs to RX-A1. Add a new row only when it describes a new, independently owned contribution at the same reference plane and band.

At this boundary, convert watts and volts into the explicitly chosen full-scale reference before comparing code-domain limits.

03 / 10

Full scale, dBFS, crest factor, and clipping margin

Does −6 dBFS average power with 6 dB crest factor already clip?

For this fixture, 0 dBFS is the average power of a 2.000 Vpp differential full-scale sine across a 100 Ω differential teaching resistance. The rail is ±1 V differential. Real ADCs can present buffered or switched, frequency-dependent inputs; this resistance is a bookkeeping reference, not an input equivalent circuit.

Derived voltage sketch, one cycle. Vdiff=V+−V−; V+=VCM+Vdiff/2 and V−=VCM−Vdiff/2. VCM is unspecified, so individual-pin limits remain an evidence request.

\begin{aligned}V_{\mathrm{FS,rms}}&=\frac{V_{\mathrm{FS,pp}}}{2\sqrt2}\\P_{\mathrm{FS}}&=\frac{V_{\mathrm{FS,rms}}^2}{R}\\P_{\mathrm{FS,dBm}}&=10\log_{10}\left(\frac{P_{\mathrm{FS}}}{1\,\mathrm{mW}}\right)\\P_{\mathrm{dBFS}}&=P_{\mathrm{dBm}}-P_{\mathrm{FS,dBm}}\end{aligned}

A1 voltage is across the declared real differential resistance. dBm references 1 mW; dBFS references this sine power. Keep full precision until display.

Independent full-scale conversion · 2 Vpp differential / 100 Ω
Calculation	Checked result
Full-scale RMS voltage	0.707106781 V
Full-scale sine power	5.000000000 mW = 6.989700043 dBm
Wanted −62.5 dBm	−69.489700043 dBFS; not −62.5 dBFS
Quantizer voltage step	q = 2/4096 V = 488.281250 µV
Zero-mean balanced pin swing	Each pin ±0.5 V about VCM for the full-scale sine; VCM remains unknown.

Our illustrative signed quantizer uses N-bit two’s-complement codes −2^(N−1)…2^(N−1)−1, step q=Vspan/2^N, and code centers at kq across the differential span. Round to nearest, with exact half ties away from zero, then saturate to the endpoint codes. The most positive code center is Vspan/2−q; the analog rail definition remains Vspan/2. The full-scale-sine SNR is an ideal benchmark at the range limit, not a guarantee of undistorted endpoint behavior in a finite record.

\begin{aligned}M_{\mathrm{rail}} &= 10\log _{10}2 - P_{\mathrm{avg,dBFS}} - \mathrm{CF} \\ M_{\mathrm{reserve}} &= M_{\mathrm{rail}} - \mathrm{reserve}\end{aligned}

CF=20log₁₀(Vpeak/Vrms)=10log₁₀(Ppeak/Pavg) for the SAME composite waveform/reference. The sine rail peak contains twice its reference mean power.

Think about itFor a supplied composite average of −6 dBFS, CF=6 dB and a 3 dB reserve, what is left?

Answer

Mrail=3.010299957−(−6)−6=3.010299957 dB. After subtracting the reserve once, 0.010299957 dB remains. The incorrect expression −Pavg−CF would report zero before reserve and wrongly reject this scalar example. At 0 dBFS average, the rail margin is −2.989700043 dB: the declared peak exceeds the rail.

Those exact anchors prescribe the composite average. In the live blocker exercise, sum wanted, analog noise and the −6 dBFS blocker in linear power before applying the declared composite crest factor. The extra weak powers make its margin fractionally smaller. Independent averages may sum, but a new crest factor is not derivable by summing each component’s crest factor.

Common misconceptiondBFS has a universal voltage value, and a crest factor gives clipping probability.

Full-scale conventions vary by converter, channel and measurement. A scalar crest factor gives one deterministic peak/mean relation. Clipping probability needs an amplitude distribution or a finite sample population, its observation interval and filtering. No probability is inferred here.

Go deeperDifferential validity does not establish common-mode validity

Vdiff=V+−V− and VCM=(V++V−)/2 are independent coordinates. Both pins must stay inside their allowed ranges while the common-mode control loop settles. A permitted 2 Vpp differential swing around the wrong VCM can violate a pin limit. Ask for operating ranges and recovery behavior, not only absolute maximum ratings.

The next comparison must be just as explicit about its numerator, denominator and test band.

04 / 10

SNR, SINAD, ENOB, SFDR, and noise density

Which error denominator does each converter metric include?

Sine metrics · align input amplitude, analog fin, fs, band, supplies, temperature and processing
Metric	Numerator / denominator	What it cannot prove
SNR	Named sine power / integrated noise, with the stated harmonics/DC exclusions	Distortion, clipping or every weak-signal waveform.
SINAD	Named sine power / noise plus distortion in the stated test band	A fresh independent error to add to its included noise, quantization or timing.
ENOB	(SINAD−1.76)/6.02 under the pinned rounded sine convention	Physical code count, DC accuracy, or universal effective bits.
SFDR	Named carrier power / largest discrete spur in the stated search band	A noise floor or the frequency of that spur. dBc and dBFS use different references.
Noise density	Noise power per Hz, with one/two-sided reference and shape specified	Integrated noise until weighted by the actual receive filter.

The default mode is an ideal quantizer benchmark. With uniform, decorrelated error, the q²/12 model supports white-noise integration. This is not a model of every periodic input or every real ADC. The supplied-performance mode uses a separate synthetic row, and the disjoint-contributor mode sums independently owned same-band powers. The three are alternatives.

\begin{aligned}\mathrm{SNRq} \approx 6.02N + 1.76 &= 74.00 \mathrm{dB} \\ N_{\mathrm{q,density}} &= -\mathrm{SNRq} - 10\log _{10}(\frac{f_{s}}{2}) \\ N_{\mathrm{q,B}} &= N_{\mathrm{q,density}} + 10\log _{10}B \\ G_{\mathrm{process}} &= 10\log _{10}[\frac{\frac{f_{s}}{2}}{B}]\end{aligned}

One real ADC, 0…fs/2 Nyquist band; full-scale sine. The portfolio deliberately rounds both coefficients. Exact q²/12 constants give about 74.008112 dB at 12 bits.

Independent ideal 12-bit / 80 MS/s / 20 kHz anchors · conditional white noise, input-referred at A1
Quantity	Checked result
Rounded full-scale sine SNR	74.000000000 dB over 40 MHz
One-sided quantization density	−150.020599913 dBFS/Hz
White-noise process gain	33.010299957 dB
20 kHz quantization noise	−107.010299957 dBFS = −100.020599913 dBm
Wanted / quantization only	−69.489700043 − (−107.010299957) = 37.520599913 dB
Analog-noise addition	10log₁₀[1 + 10^((−100.020599913 + 85.665007875)/10)] ≈ 0.156451 dB; compare with 0.5 dB allocation.
Synthetic sine ENOB	SINAD=65.00 dB → (65−1.76)/6.02 = 10.504983389 bits

Think about itThe synthetic sine row already includes timing, noise and distortion. Should a budget add its 65 dB SINAD, 74 dB ideal quantization and 64.036 dB aperture-jitter ceiling?

Answer

No. Its denominator already contains the relevant ADC quantization and timing errors. The three-way sum counts them again. Preserve the row’s 65 dB SINAD at its test conditions; deriving a narrowband weak-signal budget still needs noise and spur spectra. The rejected sum has no valid physical ownership ledger.

\mathrm{SNR}_{\mathrm{total}} = -10\log _{10}[\sum 10^{-\frac{\mathrm{SNR}_{i}}{10}}]

Only independent contributions with the SAME sine numerator and measurement band. Alternatively convert each contributor to absolute same-plane, same-band noise power before adding.

Never put a full-scale quantization SNR, the gateway’s weak-signal analog SNR and a blocker-relative dBc spur directly into that sum. First align references and bands; keep deterministic spurs separate unless a precisely defined SINAD denominator includes them.

Think about itA −6 dBFS test tone has SFDR 78 dBc, and its spur lands on the wanted channel. Does 33.0103 dB process gain lower the spur?

Answer

No. Under that exact supplied test, the spur is −6−78=−84 dBFS. A coherent in-channel product passes through the wanted filter with the signal; it gets no white-noise process gain. If the spur frequency or the −6 dBFS operating-condition row is missing, wanted-channel impact is unknown.

Common misconceptionHigh SFDR guarantees high SNR/SINAD, and quantization error is always white Gaussian noise.

A converter can have small discrete spurs but substantial broadband noise. Quantization error can correlate with a low-level periodic signal and concentrate into harmonics. Check both the spectrum and the assumptions behind a density model.

Analog Devices MT-001 provides the ideal derivation and correlation caveat. The figures here are independently derived local examples. Now check whether analog origins remain separable at all.

05 / 10

Sample rate, alias plan, and analog filters

Can a 2.45 GHz signal fit through an 80 MS/s real sampler?

A single narrow RF channel can have valid bandpass-sampling geometry if the front end selects the correct analog support and rejects its alias images. Sample rate alone does not prove usable analog input bandwidth. The RF80 candidate therefore has a synthetic 3000 MHz input-bandwidth bound, distinct from its 80 MS/s code rate.

\begin{aligned}f_{\mathrm{wrap}}&=f_{\mathrm{in}}-f_s\left\lfloor\frac{f_{\mathrm{in}}+f_s/2}{f_s}\right\rfloor\\f_{\mathrm{alias,real}}&=|f_{\mathrm{wrap}}|\end{aligned}

Exact 05.2 algorithm, frequencies in Hz. Signed wrap uses [−fs/2,+fs/2); a real positive-frequency plot then folds by magnitude. Split intervals at every kfs/2 boundary and retain open wrap endpoints.

Independent sample aliases · one real channel, support width 13.5 kHz
A1 / sample rate	Signed / positive center	Real A0 support / orientation
100 MHz / 80 MS/s	+20 / 20 MHz	19.993250…20.006750 MHz; preserved →
2450 MHz / 80 MS/s	−30 / 30 MHz	29.993250…30.006750 MHz; reversed ←
2450 MHz / 3000 MS/s	−550 / 550 MHz	549.993250…550.006750 MHz; reversed ←
2430 MHz CW / 80 MS/s	+30 / 30 MHz	Coincides with RF80 wanted center if both analog origins pass.
39.990…40.010 MHz / 80 MS/s	Crosses Nyquist boundary	Two real segments overlap at 39.990…40.000 MHz; a center-only test misses the failure.

The low-IF tracking pass region is 99.980–100.020 MHz, with transition edges 99.900/100.100 MHz. Both RF presets use 2449.980–2450.020 MHz and 2449.900/2450.100 MHz. These are geometric requirements only. They say nothing about achieved attenuation, filter order, tuning error, acquisition tolerance or distortion. An upstream 2430 MHz interferer can be conditionally rejected by the narrow RF selection; if it reaches A1 with the wanted signal in RF80, the collision remains a failure.

A full 100 MHz simultaneous capture replaces that narrow selection. RF80 cannot preserve a general 100 MHz band in its 40 MHz real interval. RF3000 can have a disjoint folded interval, but still fails the default jitter target and sample-data limit. It cannot send all of that captured band into an 80 kcomplex-sample/s stream.

Common misconceptionOversampling eliminates analog filters, and a digital filter can repair analog overload or an alias collision.

Every analog signal and noise contribution admitted at the pins participates in sampling. Once two origins coincide or peaks saturate, a downstream filter cannot reconstruct which information was lost. Higher fs changes geometric spacing; it does not create an ideal input filter.

Go deeperWhy decimation needs filtering first

Keeping every Mth sample creates a new rate and a closer periodic spectrum. Before discarding samples, attenuate content that would wrap onto the retained band. The low-IF chain first selects and translates the +20 MHz alias to complex baseband, corrects orientation when required, and filters before reaching 80 kcomplex-sample/s. Nominal decimation factors are 1000 from 80 MS/s and 37500 from 3000 MS/s; these ratios do not design a multistage filter or its stopband.

For u=I+jQ, the signed interval has width fs. Two physical quadrature ADCs can preserve sign when the upstream quadrature representation is valid. One real ADC plus a DDC has a different analog alias ambiguity. The planner changes the interval, per-branch white-noise accounting and physical channel count when I/Q is selected; it never silently mixes at RF to reduce fin for jitter.

Three canonical candidates · same selected 13.5 kHz channel, 20 kHz ENBW, one 12-bit ADC / 16-bit transport, 1 ps total
Candidate / analog bound	A0 alias / orientation	Noise benchmark / jitter	Transport / decision
Low IF · 100 MHz / 80 MS/s; 500 MHz synthetic bound	20.000 MHz signed; 20.000 MHz real; preserved	-100.020599913 dBm ideal quantization at A1; 64.036402633 dB sine jitter ceiling. RF analog-noise transfer needs new provenance.	1.600 Gbit/s; no supplied scalar failure; driver/filter/spur/power evidence open.
RF undersampling · 2450 MHz / 80 MS/s; 3000 MHz synthetic bound	-30.000 MHz signed; 30.000 MHz real; reversed	-100.020599913 dBm ideal quantization at A1; 36.253080946 dB sine jitter ceiling. RF analog-noise transfer needs new provenance.	1.600 Gbit/s; Jitter-only sine ceiling; driver/filter/spur/power evidence open.
RF high rate · 2450 MHz / 3000 MS/s; 3000 MHz synthetic bound	-550.000 MHz signed; 550.000 MHz real; reversed	-115.760912591 dBm ideal quantization at A1; 36.253080946 dB sine jitter ceiling. RF analog-noise transfer needs new provenance.	60.000 Gbit/s; Jitter-only sine ceiling, Sample-data transport; driver/filter/spur/power evidence open.

MT-002 and TI SBAA328 frame the sampling and RF-system trade. A geometric pass now needs a timing budget.

06 / 10

Aperture jitter creates a frequency-dependent ceiling

Why does a low-frequency alias still need a clock suited to the original RF slope?

For a small sample-time error Δt, the voltage error is approximately (dv/dt)Δt. A sine’s slope grows with analog fin. This produces a sine-reference ceiling, independent of nominal bit count. The RMS timing terms must refer to the sampling instant and must be disjoint before using root-sum-square.

\begin{aligned}\sigma_t&=\sqrt{\sigma_{\mathrm{external}}^2+\sigma_{\mathrm{aperture}}^2}\\\mathrm{SNR}_j&=-20\log_{10}(2\pi f_{\mathrm{in}}\sigma_t)\\\sigma_{t,\max}&=\frac{10^{-\mathrm{SNR}_{\mathrm{target}}/20}}{2\pi f_{\mathrm{in}}}\end{aligned}

fin in Hz, σt in seconds, sine input, small uncorrelated timing error. Controls use ps and are converted once. The live small-error screen uses 2πfinσt≤0.1; larger arguments are outside this approximation.

A1 sine reference; derived small-error ceiling, not a 20 kHz noise spectrum. Traces hold analog fin fixed. Neither curve changes when only fs changes. Omitted portions exceed the disclosed small-error bound.

Independent timing anchors · separate full-band sine exercise
Condition	Checked result
Independent .800 ps external / .600 ps device	Total 1.000000000 ps; supplied-total mode instead replaces both.
100 MHz analog / 1 ps	64.036402633 dB jitter-only ceiling
2450 MHz analog / 1 ps	36.253080946 dB jitter-only ceiling at both 80 and 3000 MS/s
Independent 74 dB quantization + 100 MHz jitter	63.619153814 dB, full-scale sine / full fs/2 band
Independent 74 dB quantization + 2450 MHz jitter	36.252351394 dB, full-scale sine / full fs/2 band
2450 MHz analog / 60 dB jitter target	Total ≤0.064961201 ps (≈64.961 fs); timing allocation only.

The 60 dB RF allocation is already below the .600 ps device aperture assumption. Choosing a quieter external clock cannot overcome that component in this fixture. Raising fs to 3000 MS/s improves ideal white-quantization density and changes data load, but leaves the analog-frequency timing ceiling unchanged.

Total jitter does not establish narrowband blocker desense. The same integrated RMS timing error can come from near-carrier noise, far-offset noise or discrete modulation. Without its spectrum and transfer into the 20 kHz wanted band, no in-band jitter-noise number is available.

Go deeperA scalar integral loses the location of the timing error

For small phase modulation, 04.7 maps a one-sided SSB phase-noise density through the clock distribution and integrates over named offset bounds. Random phase variance is 2∫Llinear(foffset)dfoffset; converting it to time also needs the carrier frequency of that clock. Equal integrals can have very different offset distributions. In a blocker experiment, the relevant weighted spectral error around the blocker must land inside the wanted filter’s response.

Two uncorrelated timing contributions can RSS. Correlated terms need covariance: σtotal²=Σσᵢ²+2Σcov(δtᵢ,δtⱼ). A vendor RMS total or sine performance row may already include the internal aperture and test clock. Keep its integration bounds and inclusion list; do not add the same component again. See MT-007 and MT-008.

Common misconceptionClock jitter is a fixed dB loss; use the sample rate or sampled alias in the formula.

Timing error acts on the analog waveform before alias relabeling. Use analog fin. The ceiling is not an input-level-independent additive power floor and cannot be inserted unconverted into the weak-signal noise ledger.

Clock quality cannot rescue a driver that fails to present the required voltage at the sampling instant.

07 / 10

Driver settling, common mode, kickback, and input network

Does a driver with a wide −3 dB bandwidth necessarily settle to half an LSB?

The input network is an interface contract. A switched-capacitor input may draw transient charging current and return kickback into the antialias filter. A buffered ADC has another input model. In both cases, the driver sees source/load impedance, feedback dynamics and a common-mode requirement. Wide small-signal bandwidth alone does not establish accurate acquisition after a large step.

Driver review · evidence required at A1, not inferred from 100 Ω teaching power
Boundary	Ask for	Failure to screen
Voltage / common mode	Differential full scale; per-pin min/max; VCM range and control settling, supplies	A valid differential signal may still violate a pin limit.
Acquisition	Actual track/acquisition time, input network, data-sheet timing definition	Sample interval is not automatically available settling time.
Source / load	Source impedance, ADC capacitance, kickback, filter load and damping	Loading or resonance can change bandwidth and distortion.
Dynamic fidelity	Settling vs step, frequency/amplitude SNR/SINAD/SFDR and common-mode behavior	Bandwidth or slew rate alone misses error tails.
Noise / current	Input/output referred noise, bandwidth, provenance and transient current	Double-counted driver noise or unsupported supply demand.

\begin{aligned}&\exp (-\frac{T_{\mathrm{acq}}}{\tau }) \le 2^{-(N+1)} \\ &\frac{T_{\mathrm{acq}}}{\tau } \ge (N+1)\ln 2 \\ N&=14 \to 10.397207708 \text{time constants}\end{aligned}

Illustrative FIRST-ORDER full-span step only. N bits, residual as fraction of full-scale span; Tacq and τ in the same time units. No real acquisition model is inferred.

A hypothetical 10 ns acquisition interval would require τ≤0.961796694 ns in that single-pole model. A real driver/ADC combination can also have slewing, multiple poles, switching charge and nonlinearity. A first-order −3 dB bandwidth is only one property of this toy response.

As a separate example, TI THS4541 SLOS375B distinguishes small-signal, large-signal and settling tests. Its 5 V table uses 25 °C, G=2, 2 Vpp differential output, 402 Ω feedback and 499 Ω load; the 0.1% settling row specifies an 8 ns typical result for a 2 V step with a 2 ns transition. That is not a half-LSB 14-bit guarantee and is not this gateway’s ADC loading.

Common misconceptionThe ADC input is a fixed resistor, and driver selection follows from −3 dB bandwidth alone.

The 100 Ω reference only converts voltage to teaching power. Use the chosen converter’s input model and the driver’s large-signal/transient conditions to test acquisition, noise, distortion and current.

The transmit direction carries the same discipline across a different conversion: digital codes become a held analog waveform.

08 / 10

DAC images, zero-order hold, and reconstruction

Where do unwanted DAC replicas first exist, and which filter can reject them?

Follow 05.5’s transmitter handoff from D3 numerical scaling through interpolation and an optional digital NCO to A0 codes. A1 is the held analog waveform, including images and real converter errors. Reconstruction filtering acts there; a later analog IQ/LO stage produces R0. A digital frequency translation does not change the DAC’s analog hold response or eliminate its images.

D3: define I+jQ, signed numeric range, waveform peaks and output scaling.
A0: interpolate/filter, apply the declared NCO sign, round or saturate, and emit codes at the physical DAC rate.
A1: the hold produces a sinc envelope and replicas; real DAC output current, compliance and spur levels need device evidence.
Reconstruction: preserve the desired support and attenuate images before any later mixing creates unwanted RF products.
R0: with sRF=Re{u exp(+j2πfct)}, a positive complex offset appears above fc. A real-DAC mirror at fs−f has reversed spectral orientation; retain that transformation when choosing an image or later LO side.

A1 ideal ZOH amplitude, normalized to its DC response. Nonnegative spectrum; conjugate negative images implied. The dashed rectangle names a reconstruction pass region, not achieved rejection or real DAC SFDR.

\begin{aligned}|H_{\mathrm{ZOH}}(f)| &= |\frac{\sin (\frac{\pi f}{f_{s}})}{\frac{\pi f}{f_{s}}}| \\ &\text{nearest positive replicas}: f_{s}-f_{\mathrm{out}}, f_{s}+f_{\mathrm{out}}\end{aligned}

Separate ideal DAC example: fs=80 MS/s, fout=10 MHz. Magnitude relative to DC; amplitude droop uses 20log₁₀, not a power-ratio logarithm applied directly to amplitude.

Independent ideal DAC anchors · no reconstruction rejection or actual spur level supplied
Quantity	Checked value / implication
Desired output	10 MHz; ideal support represented by a tone.
Nearest positive replicas	70 MHz (mirrored) and 90 MHz (same orientation); conjugate negative frequencies implied.
10 MHz ZOH amplitude droop	−0.224404502 dB relative to DC; magnitude ≈0.974495358.
Reconstruction requirement	Pass 10 MHz signal and attenuate 70/90 MHz images to the system allocation; required attenuation/order unknown.
Practical DAC errors	Output compliance, glitch, clock feedthrough, nonlinear spurs and supply/current conditions unknown.

Common misconceptionA clean digital waveform guarantees a clean analog DAC output.

The A0 code spectrum and A1 analog spectrum are different boundaries. Reconstruction and converter/clock evidence remain necessary even with exact arithmetic.

Before those codes leave the digital path, define what happens when an arithmetic result no longer fits its word.

09 / 10

Word length, scaling, overflow, data rate, and latency

Are converter bits, accumulator bits, transported bits and two I/Q coordinates the same resource?

State signedness, total width, binary point, rounding and overflow policy at every operation. Here Q1.15 means a 16-bit two’s-complement number with one sign/integer bit and fifteen fractional bits: [−1, 1−2^−15]. Other Q-format naming conventions exist, so the bit layout is the contract.

Deterministic Q1.15 overflow exercise · exact arithmetic, no random-noise claim
Operation / policy	Code / value	Consequence
0.75 + 0.75	24576 + 24576 = 49152 → exact 1.5	Needs an extra integer bit at the same binary point.
Saturate to signed 16 bits	32767 → 0.999969482421875	Clips at the positive representable endpoint.
Wrap modulo 2^16	0xC000 interpreted signed → −16384 → −0.5	Large sign-changing error; not interchangeable with saturation.
Rounding / truncation	Inputs here are exact Q1.15 values; no fractional bits are discarded by addition	Other operations must state tie-breaking, truncation bias and scale.

An N-bit by M-bit fixed-point product can need N+M bits before rescaling. Summing K bounded products may need up to ceil(log₂K) additional guard bits beyond the product width, depending on the actual bounds. Coefficient quantization, accumulator growth and output rounding affect response and distortion. They do not increase the ADC’s physical resolution merely because the transport word is wider.

\begin{aligned}R_{\mathrm{raw}}&=f_s W_{\mathrm{transport}}C_{\mathrm{physical}}\\R_{\mathrm{8b/10b}}&=R_{\mathrm{raw}}\frac{10}{8}\\R_{\mathrm{D3}}&=f_{\mathrm{complex}}(W_I+W_Q)\end{aligned}

A0 raw payload counts scalar physical-channel words. Encoded aggregate omits any extra framing. D3 counts I and Q separately within every complex sample.

Independent transport and time anchors · nominal fixture
Boundary	Checked arithmetic	Condition
One real ADC raw A0	80 MS/s × 16 = 1.280 Gbit/s	12 nominal bits inside each transported 16-bit word.
Illustrative encoded A0	1.280 × 10/8 = 1.600 Gbit/s	Aggregate; actual lanes, framing and sync omitted.
Two physical I/Q ADCs	2 × 1.600 = 3.200 Gbit/s	Per-branch full scale unchanged; violates 2 Gbit/s local limit.
One real ADC + complex DDC	A0 remains 1.600 Gbit/s in this external raw-data example	Complex downstream processing does not double physical ADC channels.
D3 selected complex stream	80,000 × (16+16) = 2.560 Mbit/s	Unframed; after valid filtering and decimation.
Pipeline component	12 / 80 MHz = 150 ns	Converter clocks only.
Input-buffer span	1024 / 80 MHz = 12.8 µs	Span is not end-to-end latency or each sample’s wait.
RF3000 encoded A0	3000 MS/s × 16 × 10/8 = 60 Gbit/s	Fails the same 2 Gbit/s local boundary.

Common misconceptionOversampling and decimation make data rate, latency and power free.

Raw capture, transport, filter arithmetic, buffering and clock distribution still cost resources. Filter delay, scheduling and interface latency must be allocated separately. Power requires operating-condition current data; this lesson supplies no energy-per-sample coefficient and infers no watts from bits or fs.

The decision now has enough structure to identify a viable next investigation without pretending the hardware is already qualified.

10 / 10

Choose the gateway conversion and clock boundary

Which option would you carry forward, and what evidence could still reverse that choice?

Start with the low-IF preset. Inspect its narrowband noise and full-band sine timing results separately. Load the −6 dBFS blocker corner, then the 0 dBFS stress. Compare RF80 and RF3000. Enable the 2430 MHz threat and admit both analog origins to reproduce RF80’s collision. Finally, switch performance modes and attempt to add RX-DRV again: the ownership test must prevent a misleading sum.

Class 1 · a converter boundary decision

Converter & Clock Boundary Planner

Choose a candidate, predict its limiting condition, then inspect the evidence. Apply edits to update the contract. Presets restore every defining input; view and key-point changes leave the allocation untouched.

Architecture and capture

Architecture presetAll three presets restore the full fixture, including evidence modes, blockers off and 1 ps timing.

Capture requestFull capture replaces the selected support and filter pass region. It cannot silently reuse the 80 kcomplex/s handoff.

Analog input center (MHz)0.001…6000 MHz; step 0.001.

A0 rate per physical ADC (MS/s)1…5000 MS/s; step 0.001.

Selected total signal support (MHz)0.001…100 MHz; step 0.000001. Default 0.013500 MHz; full-band mode instead uses 100 MHz.

Wanted integration ENBW (kHz)1…1000 kHz; step 0.001.

Synthetic analog-input bound (MHz)1…6000 MHz; step 0.001.

Physical sampling arrangementI/Q requires pairs. Selecting I/Q raises an odd physical count to the next even count; analog fin is unchanged. This presumes analog quadrature already exists at A1.

A1 levels, full scale and blocker corners

Per physical branch · actual network remains conditional

A1 wanted / I average power (dBm)-180…20 dBm; step 0.1.

A1 receiver noise / I (dBm)-180…20 dBm; step 0.1. Exact inherited −85.665007875 dBm is also accepted. Editing declares new A1 evidence at the stated band.

Receiver-noise evidence ENBW (kHz)1…1000 kHz; step 0.001.

Receiver-noise provenanceInherited value applies only at 100 MHz IF and 20 kHz. A new band or RF plan needs a new A1 analog-noise allocation; it is not silently scaled.

Full-scale differential sine (Vpp)0.5…4 Vpp; step 0.01.

Differential teaching resistanceUsed only to relate differential RMS voltage to power. This is not a claim that the ADC input is resistive.

Composite peak / average ratio (dB)3.010299957…15 dB; step 0.01. Exact sine limit 3.010299957 dB is also accepted. Composite crest factor includes the admitted waveform population.

Separate peak reserve (dB)0…12 dB; step 0.01.

A1 blocker exerciseDefault exercise −6 dBFS average at 101 MHz; stress 0 dBFS. Crest applies to the entire admitted composite.

Blocker average per physical branch (dBFS)-120…0 dBFS; step 0.1.

Blocker analog frequency (MHz)0.001…6000 MHz; step 0.001.

2430 MHz upstream alias threatRF80 maps 2450 and 2430 MHz to the same positive 30 MHz. Amplitude is unknown.

Analog front-end selectionTracking regions name required selection only. Both admitted preserves RF80’s collision failure; downstream processing cannot repair it.

Performance and timing ownership

Nominal converter width (bits)6…18 bits; step 1.

Performance modelThese modes are mutually exclusive. Specified SINAD is never summed with ideal quantization or already-included timing.

Timing input modeRSS only for independent timing errors. The total mode excludes the stored components.

External RMS jitter (ps)0.03…100 ps; step 0.01.

Device aperture RMS jitter (ps)0.03…100 ps; step 0.01.

Timing independenceUnknown covariance suppresses the combined timing ceiling. A phase-noise integral already including aperture cannot be added again.

Extra driver noise and interface evidence

05.3 already includes RX-DRV noise

New driver-noise contributionA new stage requires its own source, same-plane bandwidth and disjoint inclusion. This is not a second RX-DRV allocation.

Extra driver-noise value (dBm or dBm/Hz)-220…20 dBm or dBm/Hz; step 0.01.

Extra-driver evidence bandwidth (kHz)1…1000 kHz; step 0.001.

Driver value unitsNoise density and integrated noise are different units. In I/Q mode the given contribution applies separately to each branch over the signed band.

Driver ownershipUnknown/overlapping evidence suppresses the narrowband total.

Driver-noise reference planeNo implicit gain or impedance conversion.

New driver source IDUnique ID, not RX-DRV or an existing ADC source.

New driver scope and provenanceName the new stage, its noise model and exclusions, same-band conditions and source. Blank with the stage enabled suppresses the total.

Driver/interface evidence requestRecord full-scale/common-mode and per-pin limits, acquisition, source impedance, capacitance/kickback, antialias load, distortion, settling and current. This planner does not certify a network from text.

Digital transport and latency

Raw A0 payload and fixed D3 handoff

Transported raw word width (bits)8…32 bits; step 1.

Physical ADC channels (channels)1…8 channels; step 1.

Illustrative line codingAggregate rate only. Framing, lane mapping, sync and protocol-specific overhead are separate evidence requirements.

Converter pipeline length (clocks)0…1000 clocks; step 1.

Input buffer length (samples)0…65536 samples; step 1.

Local screens: aggregate encoded A0 sample-data rate ≤2 Gbit/s; jitter-only sine ceiling ≥60 dB; added ADC/driver noise ≤0.5 dB. D3, when valid, is fixed at 80 kcomplex-sample/s and 16+16 bits. No power model is supplied.

Inspect the committed support: lower edge. No dragging required.

Conditional allocation · evidence remains open

Low IF · 100 MHz / 80 MS/s. No complete hardware-feasible plan has been established.

Wanted-band jitter desense is unknown. Total RMS timing error gives a sine-reference ceiling. It does not locate a blocker’s timing-error power within the 20 kHz wanted ENBW. No spectral shape or transfer function has been supplied.

A1 full-scale sine / teaching load: 0.707106781 Vrms
6.989700043 dBm
A0 wanted / I relative to its own full scale: -69.489700043 dBFS
Analog-frequency jitter-only ceiling: 64.036402633 dB
1.000000000 ps total
Aggregate encoded A0 sample data: 1.600000 Gbit/s

Alias / filter geometrypasses supplied screen
Selected support is disjoint. Filter attenuation, tuning and stopband order remain unverified.
Analog-input bandwidthpasses supplied screen
Wanted outer edge versus 500 MHz synthetic input bound. This is a geometric screening number, not an SNR/driver guarantee or sample rate.
Full scale / deterministic peakpasses supplied screen
Real: rail 66.479096 dB, after 3 dB reserve 63.479096 dB. Composite crest factor is a supplied waveform condition; clipping probability unknown.
Added ADC / driver noisepasses supplied screen
Real: 0.156451 dB versus 0.5 dB allocation; same-band independent terms only.
Jitter-only sine ceilingpasses supplied screen
64.036403 dB versus 60 dB at ANALOG 100 MHz, 1.000000 ps total. Full-band sine exercise; wanted-band jitter noise is unknown.
Spur location / performance evidenceinspect—missing/overlapping evidence
No supplied operating-condition spur map. Nominal bits and white-noise process gain do not bound a coherent spur.
Driver / common-mode / networkinspect—missing/overlapping evidence
Supply common-mode and per-pin limits, acquisition behavior, source impedance, input capacitance/kickback, filter load, noise/distortion, settling and current evidence.
Sample-data transportpasses supplied screen
1.600000 Gbit/s aggregate versus 2 Gbit/s local limit. 1 physical channels, 16 bits, 8b10b illustrative overhead; framing/lane mapping still required.
D3 filtering / latency / powerinspect—missing/overlapping evidence
80 kcomplex-sample/s can fit after valid channel filtering; pipeline 150.000000 ns; buffer span 12.800000 µs. End-to-end latency and power require evidence.

Physical branches and full-scale reference

A1 average / deterministic peak ledger · same settings repeat for each real channel or I/Q pair
Branch	Wanted / analog noise	Composite and volts	Rail / reserve
Real	-62.500000 dBm = -69.489700 dBFS; noise -85.665008 dBm = -92.654708 dBFS over 20 kHz	-69.468796 dBFS average; 0.000237709 Vrms differential; 0.000474291 V declared composite peak	66.479096 dB to rail; 63.479096 dB after 3 dB reserve. Negative rail margin means deterministic clipping; negative reserve alone means inadequate reserve.

Peak arithmetic covers only the supplied wanted, integrated analog noise and enabled blocker. Unallocated out-of-band analog noise or additional signals can consume more headroom; the scalar crest factor must cover the complete admitted population.

One real ADC does not become two physical ADCs when a DDC creates I+jQ. Real one-sided quantization density uses fs/2; its conjugate negative support is implied.

Ideal benchmark · conditional white-error allocation

A1-referred ideal quantizer · full-scale sine reference, not a data sheet
Quantity	Result / convention
q / code interval	488.281250000 µV; 2^12 codes across 2 V differential span
Rounded / exact full-band sine SNR	74.000000000 / 74.008111550 dB; 6.02/1.76 versus exact q²/12
Per-branch density	-150.020599913 dBFS/Hz over 0…fs/2
Per-branch integrated quantization noise	-107.010299957 dBFS = -100.020599913 dBm over 20 kHz
White-noise process gain	33.010299957 dB; never a coherent-spur credit
Real wanted / quantization only	37.520599913 dB before analog noise, timing spectra and distortion
Separate full-band sine combination	63.619153814 dB for independent quantization and jitter-only errors; 0 dBFS sine, fs/2 band. Not the telemetry result.

Uniform ideal quantizer, no overload, error sufficiently decorrelated to model a flat PSD. A periodic weak input can correlate with codes; error is not automatically white, Gaussian or independent. Ideal nominal-bit arithmetic cannot certify ADC performance.

Evidence inspector · contributor ownership and totals

Real noise ownership · same-plane power sum
Source / reference	Power / band	Ownership	Included / excluded / conditions
RX-A1 / A1	-85.665008 dBm / 20.000 kHz	disjoint	RX-FE, RX-LNA, RX-MIX, RX-DRV included; ADC, CLOCK, DRV-NEW excluded. 05.3 high-gain matched analog ledger, 20 kHz, 100 MHz IF; RX-DRV already included.
ADC-Q / A1	-100.020600 dBm / 20.000 kHz	disjoint	ADC-Q included; RX-DRV, CLOCK, DISTORTION excluded. Rounded ideal full-scale sine convention; uniform quantizer, decorrelated white error, no overload; branch band convention explicitly selected.

Narrowband totals · excludes jitter and deterministic spurs
Branch / pair	Noise	Wanted/noise and degradation
Real	-85.508556616 dBm	23.008556616 dB SNR; 0.156451259 dB added noise
Real channel	-85.508556616 dBm	23.008556616 dB wanted / noise

Alias support and filter boundaries

Derived support only, no power axis. 1 exact segment(s), positive real fold. Key point 1/3: A1 99.993250 MHz. Full table below preserves every interval, endpoint condition and orientation.

Selected key point 1/3: A1 99.993250 MHz → A0 signed 19.993250 MHz, displayed 19.993250 MHz. A0 signed center 20.000000 MHz; displayed center 20.000000 MHz. The table includes all segments even if a stress case exceeds the six drawn rows.

Exact A1 → A0 interval map · MHz; point endpoints and open Nyquist limits retained
A1 support	A0 interval	Orientation / boundary
99.993250…100.006750	19.993250…20.006750	preserved →; zone 3

Analog filter request · geometric regions only, attenuation unknown
Boundary	Required interpretation
Stop / pass / pass / stop edges	99.900000 MHz / 99.980000 MHz / 100.020000 MHz / 100.100000 MHz
Selection	40 kHz tracking pass region; 80 kHz on each side to declared transition edges.
2430 MHz lineage	Threat disabled. Enable it to reproduce RF80’s 2450/2430 MHz collision.
A1 blocker	Off by default.
Power / driver	Unknown actual input network, driver acquisition and total converter/clock/interface power.

Transport and time

A0 / D3 ledger · transported width differs from nominal bits
Boundary	Calculated result	Still required
Raw A0 payload	1.280000 Gbit/s = 80 MS/s × 16 bits × 1 channels	Raw width must contain every nominal converter bit.
Encoded aggregate	1.600000 Gbit/s; 8b10b	Illustrative line coding, not a JESD configuration. Lane count/mapping, framing and link margin.
D3 after channel filter / decimation	2.560000 Mbit/s total; 1 × (80 kcomplex/s × 16-bit I + 16-bit Q)	Only after valid filtering and spectral orientation correction. A full-band capture cannot be retained in this stream.
Pipeline	12 clocks → 150.000000000 ns	Clock domain and mode-dependent latency.
Buffer span	1024 samples → 12.800000000 µs	Span is not a guaranteed wait for every sample.
End-to-end / power	Unknown	Filter group delay, scheduling, encoding, receiver buffering, clocking and measured supply-current modes.

Derived / Illustrative · p05-m06-converter-boundary-v1; geometry p05-m02-frequency-graph-v1. No measured performance, grading or saved progress.

Local boundary record · same content as Copy

{
  "versions": {
    "model": "p05-m06-converter-boundary-v1",
    "fixture": "p05-m06-converter-boundary-v1",
    "rules": "p05-m06-boundary-screens-v1",
    "serialization": "p05-m06-contract-json-v1",
    "display": "p05-m06-display-v1",
    "alias": "p05-m02-frequency-graph-v1"
  },
  "evidence": "Derived / Illustrative; not measured",
  "input": {
    "preset": "lowIF",
    "fin": 100,
    "fs": 80,
    "width": 0.0135,
    "enbw": 20,
    "analogBW": 500,
    "capture": "channel",
    "representation": "real",
    "resistance": 100,
    "wanted": -62.5,
    "noise": -85.665007875,
    "wantedQ": -62.5,
    "noiseQ": -85.665007875,
    "noiseBand": 20,
    "noiseSource": "inherited",
    "blockerOn": false,
    "blocker": -6,
    "blockerMHz": 101,
    "aliasThreat": false,
    "filter": "tracking",
    "vpp": 2,
    "bits": 12,
    "performance": "ideal",
    "timing": "components",
    "timingOwnership": "independent",
    "extPs": 0.8,
    "aperturePs": 0.6,
    "totalPs": 1,
    "crest": 6,
    "reserve": 3,
    "snr": 67,
    "sinad": 65,
    "sfdr": 78,
    "specSource": "synthetic",
    "testAmplitude": 0,
    "testFin": 100,
    "testFs": 80,
    "testBand": 40,
    "testConditions": "Illustrative sine row; 2 Vpp differential reference, 100 Ω teaching load; nominal synthetic supplies; 25 °C; no DDC; 0–40 MHz real Nyquist band.",
    "testIncluded": "ADC quantization, internal noise, distortion, aperture and test-clock jitter are already included; upstream 05.3 analog chain excluded.",
    "spurLocation": "unknown",
    "adcNoise": -100,
    "adcBand": 20,
    "adcKind": "integrated",
    "adcId": "ADC-EXTRA",
    "adcOwnership": "disjoint",
    "adcPlane": "A1",
    "adcConditions": "Illustrative independent additive white ADC noise, per branch at the selected ENBW; excludes 05.3 chain, jitter and deterministic distortion.",
    "driverOn": false,
    "driverNoise": -110,
    "driverBand": 20,
    "driverKind": "integrated",
    "driverId": "DRV-NEW",
    "driverOwnership": "unknown",
    "driverPlane": "A1",
    "driverConditions": "",
    "driverEvidence": "",
    "word": 16,
    "channels": 1,
    "overhead": "8b10b",
    "pipeline": 12,
    "buffer": 1024
  },
  "result": {
    "valid": true,
    "input": {
      "preset": "lowIF",
      "fin": 100,
      "fs": 80,
      "width": 0.0135,
      "enbw": 20,
      "analogBW": 500,
      "capture": "channel",
      "representation": "real",
      "resistance": 100,
      "wanted": -62.5,
      "noise": -85.665007875,
      "wantedQ": -62.5,
      "noiseQ": -85.665007875,
      "noiseBand": 20,
      "noiseSource": "inherited",
      "blockerOn": false,
      "blocker": -6,
      "blockerMHz": 101,
      "aliasThreat": false,
      "filter": "tracking",
      "vpp": 2,
      "bits": 12,
      "performance": "ideal",
      "timing": "components",
      "timingOwnership": "independent",
      "extPs": 0.8,
      "aperturePs": 0.6,
      "totalPs": 1,
      "crest": 6,
      "reserve": 3,
      "snr": 67,
      "sinad": 65,
      "sfdr": 78,
      "specSource": "synthetic",
      "testAmplitude": 0,
      "testFin": 100,
      "testFs": 80,
      "testBand": 40,
      "testConditions": "Illustrative sine row; 2 Vpp differential reference, 100 Ω teaching load; nominal synthetic supplies; 25 °C; no DDC; 0–40 MHz real Nyquist band.",
      "testIncluded": "ADC quantization, internal noise, distortion, aperture and test-clock jitter are already included; upstream 05.3 analog chain excluded.",
      "spurLocation": "unknown",
      "adcNoise": -100,
      "adcBand": 20,
      "adcKind": "integrated",
      "adcId": "ADC-EXTRA",
      "adcOwnership": "disjoint",
      "adcPlane": "A1",
      "adcConditions": "Illustrative independent additive white ADC noise, per branch at the selected ENBW; excludes 05.3 chain, jitter and deterministic distortion.",
      "driverOn": false,
      "driverNoise": -110,
      "driverBand": 20,
      "driverKind": "integrated",
      "driverId": "DRV-NEW",
      "driverOwnership": "unknown",
      "driverPlane": "A1",
      "driverConditions": "",
      "driverEvidence": "",
      "word": 16,
      "channels": 1,
      "overhead": "8b10b",
      "pipeline": 12,
      "buffer": 1024
    },
    "full": {
      "rms": 0.7071067811865475,
      "watts": 0.004999999999999999,
      "dbm": 6.9897000433601875,
      "railPeak": 1,
      "pinPeakAboutCommon": 0.5
    },
    "geom": {
      "input": [
        99993250,
        100006750
      ],
      "segments": [
        {
          "input": [
            99993250,
            100006750
          ],
          "output": [
            19993250,
            20006750
          ],
          "slope": 1,
          "zone": "zone 3",
          "openHigh": false
        }
      ],
      "edges": [
        99900000,
        99980000,
        100020000,
        100100000
      ],
      "alias": 20000000,
      "signed": 20000000,
      "reasons": [],
      "boundary": false,
      "threatCollision": false,
      "threatConditional": false,
      "blockerAliases": [
        {
          "input": [
            101000000,
            101000000
          ],
          "output": [
            21000000,
            21000000
          ],
          "slope": 1,
          "zone": "zone 3"
        }
      ],
      "threatAliases": [
        {
          "input": [
            2430000000,
            2430000000
          ],
          "output": [
            30000000,
            30000000
          ],
          "slope": 1,
          "zone": "zone 61"
        }
      ]
    },
    "sigma": 1,
    "jitter": 64.0364026328377,
    "quant": {
      "snr": 74,
      "exact": 74.0081115499123,
      "step": 0.00048828125,
      "density": -150.02059991327963,
      "inBandDbfs": -107.01029995663981,
      "inBandDbm": -100.02059991327963,
      "processGain": 33.01029995663981
    },
    "branches": [
      {
        "label": "Real",
        "wanted": -62.5,
        "noise": -85.665007875,
        "wantedDbfs": -69.48970004336019,
        "noiseDbfs": -92.65470791836019,
        "composite": -69.46879563483024,
        "margin": 66.47909559147006,
        "reserveMargin": 63.479095591470056,
        "volts": 0.00023770877853425832,
        "peakVolts": 0.0004742913677466893,
        "rows": [
          {
            "id": "RX-A1",
            "dbm": -85.665007875,
            "bandwidthHz": 20000,
            "plane": "A1",
            "reference": "dBm",
            "ownership": "disjoint",
            "includes": [
              "RX-FE",
              "RX-LNA",
              "RX-MIX",
              "RX-DRV"
            ],
            "excludes": [
              "ADC",
              "CLOCK",
              "DRV-NEW"
            ],
            "conditions": "05.3 high-gain matched analog ledger, 20 kHz, 100 MHz IF; RX-DRV already included."
          },
          {
            "id": "ADC-Q",
            "dbm": -100.02059991327963,
            "bandwidthHz": 20000,
            "plane": "A1",
            "reference": "dBm",
            "ownership": "disjoint",
            "includes": [
              "ADC-Q"
            ],
            "excludes": [
              "RX-DRV",
              "CLOCK",
              "DISTORTION"
            ],
            "conditions": "Rounded ideal full-scale sine convention; uniform quantizer, decorrelated white error, no overload; branch band convention explicitly selected."
          }
        ],
        "total": -85.5085566163806,
        "issues": [],
        "added": 0.15645125861939846,
        "snr": 23.008556616380602,
        "wantedToQuant": 37.520599913279625
      }
    ],
    "totalWanted": -62.5,
    "totalAnalog": -85.665007875,
    "totalNoise": -85.5085566163806,
    "sineTotal": 63.61915381356471,
    "specMatches": true,
    "specEnob": 10.50498338870432,
    "spurDbfs": -78,
    "payload": 1280000000,
    "encoded": 1600000000,
    "streams": 1,
    "d3Valid": true,
    "d3Payload": 2560000,
    "pipelineNs": 150,
    "bufferUs": 12.799999999999999,
    "axes": [
      {
        "axis": "Alias / filter geometry",
        "status": "pass",
        "reason": "Selected support is disjoint. Filter attenuation, tuning and stopband order remain unverified."
      },
      {
        "axis": "Analog-input bandwidth",
        "status": "pass",
        "reason": "Wanted outer edge versus 500 MHz synthetic input bound. This is a geometric screening number, not an SNR/driver guarantee or sample rate."
      },
      {
        "axis": "Full scale / deterministic peak",
        "status": "pass",
        "reason": "Real: rail 66.479096 dB, after 3 dB reserve 63.479096 dB. Composite crest factor is a supplied waveform condition; clipping probability unknown."
      },
      {
        "axis": "Added ADC / driver noise",
        "status": "pass",
        "reason": "Real: 0.156451 dB versus 0.5 dB allocation; same-band independent terms only."
      },
      {
        "axis": "Jitter-only sine ceiling",
        "status": "pass",
        "reason": "64.036403 dB versus 60 dB at ANALOG 100 MHz, 1.000000 ps total. Full-band sine exercise; wanted-band jitter noise is unknown."
      },
      {
        "axis": "Spur location / performance evidence",
        "status": "inspect",
        "reason": "No supplied operating-condition spur map. Nominal bits and white-noise process gain do not bound a coherent spur."
      },
      {
        "axis": "Driver / common-mode / network",
        "status": "inspect",
        "reason": "Supply common-mode and per-pin limits, acquisition behavior, source impedance, input capacitance/kickback, filter load, noise/distortion, settling and current evidence."
      },
      {
        "axis": "Sample-data transport",
        "status": "pass",
        "reason": "1.600000 Gbit/s aggregate versus 2 Gbit/s local limit. 1 physical channels, 16 bits, 8b10b illustrative overhead; framing/lane mapping still required."
      },
      {
        "axis": "D3 filtering / latency / power",
        "status": "inspect",
        "reason": "80 kcomplex-sample/s can fit after valid channel filtering; pipeline 150.000000 ns; buffer span 12.800000 µs. End-to-end latency and power require evidence."
      }
    ],
    "status": "inspect",
    "jitterInBand": null,
    "clippingProbability": null,
    "power": null
  },
  "limitations": [
    "Jitter in wanted band requires a spectrum and transfer function.",
    "No clipping probability from a crest-factor scalar.",
    "No power estimate from bits and rate.",
    "Tracking-filter attenuation, per-pin common mode and driver acquisition remain unverified."
  ]
}

The complete default boundary, three static candidate budgets, worked calculations, checkpoint answers and synthesis are available without JavaScript. Editing/copying require JavaScript; browser print retains the explanations and results.

Synthesis · a conditional conversion contract

Carry forward the selected-channel low-IF plan.

This is a provisional architecture allocation. It has no complete hardware-feasible result until the open evidence is resolved. The default is stronger than the RF candidates against the supplied timing and data constraints, while its small extra-noise estimate depends on the stated white-quantization assumption.

Gateway A1 / A0 / D3 contract · illustrative baseline, not an ADC purchase recommendation
Owned boundary	Conditional decision / outstanding evidence
Selected plan	100 MHz A1 input; 13.5 kHz support, 20 kHz ENBW; 80 MS/s real A0; 500 MHz synthetic analog bound. Keep the 99.980–100.020 MHz tracking selection and verify its rejection.
Noise	Wanted −62.5 dBm; RX-A1 −85.665007875 dBm / 20 kHz including RX-DRV. Ideal added quantization −100.020599913 dBm; below 0.5 dB degradation allocation only under disjoint white-error assumptions.
Peak / blocker	2 Vpp differential sine, 100 Ω teaching reference, 6 dB supplied composite crest and 3 dB reserve. The −6 dBFS corner barely clears the scalar reserve; 0 dBFS clips. Need realistic distribution and gain-state evidence.
Clock	Total 1 ps allocation → 64.036403 dB at 100 MHz. Maintain external/aperture ownership; no in-band jitter-desense claim. Request offset-resolved clock error and blocker transfer.
Spur / driver	Conditional test-amplitude SFDR, spur frequencies, common mode, per-pin swing, acquisition/kickback and actual filter/driver impedance remain unknown.
Digital boundary	1.280 Gbit/s raw or 1.600 Gbit/s illustrative 8b/10b A0. Filter/translate/correct orientation before 80 kcomplex/s D3 at 2.560 Mbit/s; pipeline 150 ns and buffer span 12.8 µs are only components.
Rejected comparison	RF80 at 1 ps fails the 60 dB jitter screen. RF3000 retains that failure and adds 60 Gbit/s transport. RF80 also fails geometry if 2450/2430 MHz both reach the real ADC.
Power / latency	Supply-current operating modes, clock distribution, lane/transceiver demand, filter delay and scheduling evidence remain required. No watt or total-latency estimate invented.

Ask for evidence at the operating point.

Request SNR/SINAD/SFDR versus analog frequency and amplitude at the intended fs; full-scale and common-mode ranges; noise PSD and integration band; spur frequencies under the selected blocker; clock/aperture definitions and inclusion; input network/acquisition and driver step/load data; transport/lane mapping and latency; current versus active/standby mode, supply and temperature. Record the actual part revision, setup and exclusions with each plot.

A current official example illustrates why this matters: AD9234 Rev. B uses its own differential input ranges, 2.05 V typical common mode and 500/1000 MS/s conditions. Its AC table uses a −1 dBFS sine and full-scale-referred SNR/SINAD labels, so the reference must be converted before comparing with our tone-relative synthetic row. Its input network, sample-clock and JESD204B sections are evidence examples; it is not the fixture’s 80 MS/s, 2 Vpp converter, nor a validated 2.45 GHz choice.

One discriminating bench request: at the intended A1 driver/common-mode network, inject the weak 100 MHz wanted signal and a swept 101 MHz blocker under the selected gain state. Capture wanted-band noise/EVM, discrete spur locations and code peaks while comparing two characterized clock spectra. Record clock bounds, amplitude references, analog filter, 20 kHz receive transfer, supplies, temperature and measurement uncertainty. This separates clipping, a discrete product and clock-mediated spectral leakage; the detailed instrument procedure belongs to Path 08.

Take this conditional record to the planned system trade review. Screen the hard constraints before scoring cost or integration convenience. Antenna/channel depth belongs to Path 06, named-technology limits to Path 07, measurement method to Path 08 and implementation/layout to Path 10.

Ungraded review

Check your understanding

Answer each question in your own words, then reveal the model answer.

01Convert 2 Vpp differential across 100 Ω to full-scale dBm, then express −62.5 dBm in dBFS.
Model answer
Vrms=2/(2√2)=0.707106781 V; P=Vrms²/100=5 mW, or 6.989700043 dBm. The wanted power is −62.5−6.989700043=−69.489700043 dBFS. This is a named sine/teaching-resistance reference, not the real ADC input impedance.
02Why reject a sum of 65 dB supplied SINAD, ideal 74 dB quantization SNR and included device-aperture error?
Model answer
SINAD already includes noise and distortion at its test conditions, including whatever timing is in that test. Adding its included quantization/aperture again duplicates contributors. Keep the supplied row, or build a separate disjoint same-plane/same-band ledger. Missing ownership suppresses the total.
03Allocate total RMS jitter for a 60 dB sine ceiling at 2450 MHz. Does a 3000 MS/s rate relax it?
Model answer
σt≤10^(−60/20)/(2π×2.45×10^9)=0.064961201 ps. Raising fs alone does not change this fixed analog-frequency allocation. The default 0.6 ps aperture component already exceeds it. This ceiling gives no 20 kHz blocker-noise allocation without a timing spectrum and transfer.
04Why does RF80 fail when the front end admits both 2450 and 2430 MHz? What about full 100 MHz capture?
Model answer
At 80 MS/s, their signed aliases are −30 and +30 MHz, which both fold to positive 30 MHz for a real ADC. Their origins are inseparable after A0. Select/reject in the analog path first. A general 100 MHz capture also exceeds the 40 MHz real independent interval and self-overlaps.
05Compare one real ADC, two physical I/Q ADCs and the later D3 stream.
Model answer
80 MS/s×16 bits is 1.280 Gbit/s raw or 1.600 Gbit/s with illustrative 8b/10b. Two physical branches double the encoded aggregate to 3.200 Gbit/s. One real ADC followed by DDC is different: after valid filtering/decimation, D3 is 80,000 complex samples/s×32 bits=2.560 Mbit/s. Full scale remains per physical branch.
06Can a −6 dBFS average / 6 dB crest waveform clear 3 dB reserve? Can an on-channel spur use white-noise process gain?
Model answer
For that prescribed composite average, Mrail=3.010299957−(−6)−6=3.010299957 dB, leaving 0.010299957 dB after reserve. At 0 dBFS average it clips. No clipping probability follows. A −6 dBFS tone with supplied 78 dBc SFDR has a −84 dBFS spur at that test; an on-channel spur gets no 33.0103 dB white-noise process gain.

Sources and further study

Primary sources checked 7 September 2026. All fixtures and plots are local Derived / Illustrative models, not measured data or digitized vendor curves. No inaccessible standard clause is paraphrased as normative.

Oppenheim, Willsky and Nawab, Signals and Systems, 2nd ed., Prentice Hall, 1996, Chapters 3–7 (SIG-1 / P02-S1); MIT OCW reading record verifies the edition. Sampling/LTI foundation and further study; the full book was not available for this implementation.
Walt Kester, Analog Devices MT-001, Rev. A, October 2008, pp.1–6, Eqs.1–10 and correlation discussion. Ideal uniform quantizer, q²/12, Nyquist-band and filtered white-error assumptions. The portfolio’s rounded 6.02/1.76 rule stays distinct from exact constants.
Analog Devices MT-002, Rev. A, October 2008, Nyquist, undersampling and reconstruction discussion, Figures 2–9. Alias and DAC hold context; exact signed interval splitting reuses 05.2’s implementation.
Walt Kester, MT-007, Rev. A, October 2008, pp.3–6, Eq.6 and Figure 5. Aperture uncertainty, analog slope and timing inclusion. MT-008, Rev. A, October 2008, phase-noise integration/bounds; same timing references as 04.7.
Dean Banerjee, PLL Performance, Simulation, and Design, 5th ed., TI SNAA106C, May 2017, noise/integration chapters; 04.7 background source. The local converter timing model does not import a synthesizer’s jitter or spur fixture.
TI SBAA328, RF Sampling for Multi-band Radios, April 2019, receiver/transmitter RF-sampling system context. Used to frame converter/clock/filter tradeoffs; no vendor power or performance is imported into the synthetic presets.
IEEE 1241-2023, official record checked Active, published 6 October 2023. ADC terminology/test-method reference. Full normative text was unavailable; no clause-level compliance or successor wording is inferred.
Analog Devices AD9234, Rev. B, January 2018; current official product PDF. Tables 1–4, pp.5–9; Analog Input Considerations pp.24–27; Clock Input Considerations pp.28–29; JESD204B/latency pp.42–55. Conditions include specified maximum 500/1000 MS/s, −1 dBFS sine, default SPI, clock divider 2, nominal listed rails and 25 °C unless noted. Analog range/common mode, test normalization, buffered input, clock inclusion, output format and power are examples of required evidence. They are not the 80 MS/s fixture or a driver pairing recommendation.
TI THS4541, SLOS375B, revised February 2024; §§6.5–6.6, 7.1/7.6/7.7 and 9.2. Separate 5 V and 3 V conditions; settling, distortion, capacitive-load and ADC-interface evidence. The 5 V 0.1% settling example above is conditional typical data, not half-LSB accuracy at 14 bits.

Model/fixture p05-m06-converter-boundary-v1; rules p05-m06-boundary-screens-v1; serialization p05-m06-contract-json-v1; display p05-m06-display-v1; alias kernel p05-m02-frequency-graph-v1. Analytical dB results checked to absolute 10⁻⁶ dB, nonrounded linear values to relative 10⁻⁹, pinned frequencies within 1 Hz and integer transport exactly. Code centers, rounded coefficients, synthetic conditions, omitted spectra and conditional interfaces remain explicit in the copied/printed record.

Converters, Clocks &the Digital Boundary

Failure: high bit count, low system performance

Translate the analog distribution to converter input

Full scale, dBFS, crest factor, and clipping margin

SNR, SINAD, ENOB, SFDR, and noise density

Sample rate, alias plan, and analog filters

Aperture jitter creates a frequency-dependent ceiling

Driver settling, common mode, kickback, and input network

DAC images, zero-order hold, and reconstruction

Word length, scaling, overflow, data rate, and latency

Choose the gateway conversion and clock boundary

Physical branches and full-scale reference

Ideal benchmark · conditional white-error allocation

Alias support and filter boundaries

Transport and time

Carry forward the selected-channel low-IF plan.

Ask for evidence at the operating point.

Check your understanding

Sources and further study

Converters, Clocks &
the Digital Boundary