RF Journey

01 / 10

Failure: the carrier is correct, the waveform fails

A counter reads 2.450000 GHz. The receiver still loses a weak signal beside a blocker. What did the counter miss?

In our illustrative engineering case, the battery node and gateway use a nominal 40.000000 MHz reference. An exact frequency ratio can place the average carrier correctly while short-term phase fluctuations spread energy around it. A nearby blocker can mix with that LO noise into the wanted band; phase error can also rotate an I/Q waveform. A deterministic spur creates a different, narrow interference mechanism.

Think about itDoes exact average frequency prove a clean, spectrally usable LO?

Answer

No. The canonical fractional plan is exactly 2.450000 GHz yet rejects this lesson’s −68 dBc/side limit because a frozen comparison fixture contains a −65 dBc/side pair at ±40 MHz. Its random jitter and linear settling separately pass. Those results address different requirements.

Bring I/Q and the complex envelope, waveform-quality interpretation, conditional component models, and the mixer LO-port requirement. Feedback fundamentals are introduced here.

By the end, you will calculate a divider plan, preserve noise injection planes, integrate a bounded random mask, compare discrete tones independently, and recommend a loop region with explicit hardware unknowns. Understanding EVM explains why constellation error needs a declared reference and processing convention. We do not turn an unweighted jitter integral into a receiver EVM prediction.

Common misconceptionA correct average output frequency proves a clean LO.

A counter constrains one frequency statistic. It does not establish the offset-noise spectrum, spurs, startup, output drive, phase tracking or modulation quality.

02 / 10

How oscillation is sustained

A resonator stores and exchanges energy. Loss removes some each cycle; an active element draws DC power to replace it. In a feedback picture, a returned sinusoidal component reinforces itself when its loop phase closes and its amplitude is sustained. In a negative-resistance picture, the active element cancels resonator loss at the chosen port.

|A\beta| = 1\qquad \arg(A\beta) = 2\pi k

Steady-state sinusoidal orientation only. Aβ is a dimensionless loop amplitude ratio; phase is modulo 2π. Nonlinear amplitude dependence and the actual network determine existence and stability.

Startup needs growth from noise or a disturbance: the small-signal loop must initially overcome loss in the relevant mode. As amplitude increases, gain compression or another limiting mechanism reduces net growth. Otherwise the linear model predicts unbounded amplitude, which is a sign that the model has left its domain.

Think about itIf a small-signal loop has unity gain and zero net phase at one frequency, have you designed startup and output amplitude?

Answer

No. A marginal linear condition says nothing complete about growth from noise, competing modes, bias transitions, amplitude stabilization or nonlinear phase shift. It orients a design; it does not finish it.

Banerjee’s fifth edition separates oscillator mechanisms from the PLL that controls frequency. A crystal, LC resonator and integrated VCO have different tuning, loss and sensitivity constraints. The allocator starts with a supplied VCO mask; it does not synthesize a transistor oscillator or infer that mask from Q.

Go deeperWhy the phase condition alone is insufficient

Solving a loop equation at one frequency finds a possible oscillation condition. Selecting a stable physical mode also requires the frequency dependence of loop gain/phase and an amplitude law. A VCO’s tuning control changes the oscillation frequency; it does not imply that supply or load changes have no influence.

03 / 10

Accuracy, drift, aging, pulling, and pushing

Start with the time scale and cause of the error. A single “stability” number can otherwise hide temperature, elapsed life, rail sensitivity and random phase in one label.

Definitions · different mechanisms, different evidence
Quantity	Meaning / useful units	Condition to retain
Initial accuracy / tolerance	Initial frequency departure or permitted bound, Hz or ppm	Reference temperature, load, supply and calibration state
Temperature drift	Frequency change with temperature, ppm or Hz/°C	Temperature span and equilibrium/history
Aging	Slow change with elapsed operating/storage time, ppm over an interval	Time, temperature history and population
Pulling	Load/termination change perturbs oscillator frequency	Named output plane, reflection magnitude AND phase
Pushing	Supply change perturbs frequency, Hz/V	Rail, voltage, tuning point and modulation frequency
Deterministic modulation / spur	Repeatable frequency/phase disturbance; discrete dBc tones	Tone offsets and per-side/pair convention
Random phase noise / jitter	Statistical phase fluctuation and its bounded integral	SSB density, carrier, offset bounds and spur treatment

\begin{aligned}\frac{\Delta f_{\mathrm{out}}}{f_{\mathrm{out}}} &= \frac{\Delta f_{\mathrm{ref}}}{f_{\mathrm{ref}}} = \epsilon \\ \pm 20\times 10^{-6} \times 2.450000 \mathrm{GHz} &= \pm 49.000 \mathrm{kHz} \\ \pm 20\times 10^{-6} \times 2.550000 \mathrm{GHz} &= \pm 51.000 \mathrm{kHz}\end{aligned}

Derived fixed-divider reference sensitivity, nominal ratio without correction. ε is signed fractional frequency error; ppm=10⁶ε. Tolerance magnitude is reported separately from divider quantization.

The ±20 ppm input is an illustrative reference bound, not a guaranteed full-temperature specification. The interaction uses the nominal carrier for mask lookup, then reports the ideal fixed-ratio tolerance excursion separately. It neither adds that excursion to the programmed-frequency error nor quietly creates another acceptance gate.

Common misconceptionppm and phase noise are the same error.

ppm expresses relative frequency displacement or a stated bound. dBc/Hz is a carrier-referred spectral density at an offset. RMS jitter is a bounded random integral with a carrier conversion. None substitutes for the others.

The original-reference plane matters next: an accurate reference can still carry random phase, and its phase deviation is multiplied along with its frequency.

04 / 10

Phase noise and bounded jitter

Write an oscillator as A cos[2πfcarrt+φ(t)] and assume small random φ in radians. L(foffset) describes noise in one sideband, normalized to a 1 Hz bandwidth and referred to carrier power. A value such as −125 dBc/Hz is incomplete without the carrier, offset, SSB convention and physical plane. Review Noise for density versus integrated power.

\begin{aligned}\mathcal L_{\mathrm{linear}}(f)&=10^{\mathcal L_{\mathrm{dBc/Hz}}(f)/10}\,\mathrm{Hz}^{-1}\\\sigma_\phi^2&\approx2\int_{f_{\mathrm{low}}}^{f_{\mathrm{high}}}\mathcal L_{\mathrm{total,linear}}(f)\,\mathrm{d}f\\\sigma_t&=\frac{\sigma_\phi}{2\pi f_{\mathrm{carr}}}\end{aligned}

Pinned convention: foffset>0 in Hz, fcarr in Hz, φ in rad. Sφ,one-sided=2Llinear rad²/Hz; equivalently Sφ,two-sided=Llinear at ±offset. Small-angle phase modulation, random density only.

The factor of two accounts for both sidebands under this mapping; it is not an extra instrument correction to apply indiscriminately. ADI MT-008 provides the oscillator-to-jitter interpretation. Our masks, interpolation and quadrature below are frozen local examples, not data extracted from that tutorial.

canonical-2p4-v1 · Illustrative one-sided SSB masks, dBc/Hz (1 Hz), 10 Hz–20 MHz; no spurs, no extrapolation
Positive offset (Hz)	Original 40 MHz reference	VCO output	PFD proxy at canonical final output
10	-80	-35	-130
100	-110	-65	-135
1000	-135	-90	-140
10000	-150	-112	-145
100000	-155	-125	-150
1000000	-158	-140	-155
10000000	-160	-155	-158
20000000	-160	-158	-158

These tables are noise-valid only for exactly 40.000000 MHz nominal original reference, 5.000000–40.000000 MHz PFD, and both nominal VCO and final output in 2.350000–2.550000 GHz, including endpoints. The VCO table is deliberately flat across that carrier interval. The PFD table is stored at canonical N/D=61.25; its fixed input-equivalent proxy is an assumption, not a physical noise law. Buffer floor is −165 dBc/Hz.

Go deeperReproduce the numerical integral

Interpolate each table in dB linearly against log₁₀ offset, retaining every knot exactly and rejecting extrapolation. Evaluate contributor transfer functions directly at 4097 log-spaced nodes fi=10×2000000^(i/4096) Hz, i=0…4096, with endpoints exactly 10 Hz and 20 MHz. Sum linear densities. Integrate trapezoids in ordinary Hz, not log Hz.

For changed bounds, keep only base nodes strictly inside, insert both bounds once, and evaluate masks and transfer at those bounds. The separate 8193-node check uses denominator 8192 and the identical clipping rule. Relative area convergence is below 2×10⁻⁵; no rounded UI number enters the integral.

After the default 100 kHz/ζ=0.70 loop mappings introduced below, the one-sided area is 1.886596178×10⁻⁴. Twice that is phase variance: σφ=0.019424707 rad ≈1.1129° RMS; σt=1.26185 ps at the final 2.450000 GHz output, over 10 Hz–20 MHz, random-only SSB bookkeeping. Including a different offset span changes this result.

Common misconceptionIntegrated jitter is meaningful without carrier, bounds or spur treatment.

Its time value depends on the carrier and its phase variance depends on the integration interval. A discrete dBc tone is not a dBc/Hz density sample. A quoted “1 ps” with those conditions missing cannot be compared reliably.

Now identify where each noise contribution enters the loop; otherwise a correct integral can still integrate the wrong spectrum.

05 / 10

Inside the PLL loop

Informative block orientation, redrawn for this lesson. Feedback is taken before the output divider D. R/N/D are dimensionless; f is Hz; Kφ and Kv conventions are defined here. The normalized teaching kernel does not choose a physical charge pump, filter or VCO gain.

Original reference → R dividerThe original oscillator’s phase is divided by R. Its comparison frequency is fPFD=fref/R.
PFD / charge pump → loop filterThe phase/frequency detector compares divided reference and feedback. Its correction current passes through a transimpedance Z(s); the resulting control-node voltage tunes the VCO. Kφ is A/rad here, not the raw pump-current setting.
VCO → N feedback dividerWith Kv in Hz/V, the small-signal phase gain is 2πKv/s rad/V. Phase is the time integral of instantaneous angular frequency. Feedback phase divides by N.
VCO → output divider D → buffer → real LO loadThe ideal final frequency is fVCO/D. Buffer additive noise and delivered LO power belong to different models. A real connecting network can change power and pulling.
Comparator → lock observationA detector’s selected digital criterion is an observation of its loop state. It is not a phase-noise or spur analyzer at the mixer load.

ADI’s PLL fundamentals supplies this block orientation. Near an operating point, linearize the phase detector, VCO gain and loop network. The kernel then transfers small perturbations about that state. Nonlinear acquisition, charge-pump saturation, reference sampling, quantization bitstreams, cycle slips, calibration and rail limits lie outside it.

Think about itIf the output divider changes, should the VCO mask be interpreted at the new output plane without scaling?

Answer

No. An ideal divider reduces phase excursions by D and phase-noise density by D²: subtract 20log₁₀D dB. Its own additive noise is extra. The final time-jitter conversion uses the actual divided carrier.

06 / 10

Divider ratio, PFD rate, and integer-N channel grid

\begin{aligned}f_{\mathrm{PFD}} &= \frac{f_{\mathrm{ref}}}{R}\qquad f_{\mathrm{VCO}} = N f_{\mathrm{PFD}} \\ f_{\mathrm{out}} &= \frac{N f_{\mathrm{ref}}}{R D}\end{aligned}

Exact nominal frequency definitions; N is the programmed average feedback ratio, R and D positive integer division. All frequencies in Hz.

Integer N makes output steps fPFD/D. At R=D=1, a 40 MHz reference gives 2.440000 GHz for N=61 and 2.480000 GHz for N=62. The 2.450000 GHz target is off-grid: the lower nearest candidate is −10.000 MHz from target, while the upper is +30.000 MHz. A 10 MHz target step is only ¼ of the 40 MHz quantum, so step-only raster feasibility fails as well.

R=8 changes fPFD to 5 MHz. N=490 then produces exactly 2.450000 GHz, and a 10 MHz channel step is exactly two integer quanta. This is a different comparison rate and divider plan, not just a different display format.

\begin{aligned}&\text{Original reference} \to \mathrm{output}: 20\log _{10}[\frac{N}{R D}] \\ &\text{PFD comparison input} \to \mathrm{output}: 20\log _{10}(\frac{N}{D}) \\ &\text{VCO output} \to \text{divided output}: -20\log _{10}D\end{aligned}

Ideal phase-transfer scaling before loop shaping, by named injection plane. Original reference includes division by R; a mask already at the comparison input does not.

At D=1, the original crystal-to-output ratio is 61.25 for both exact plans. Both therefore multiply its phase-noise density by 35.742122 dB before loop shaping. The integer plan’s 20log₁₀490=53.803922 dB is correct for a PFD-input mask, not for the original 40 MHz crystal mask. The R divider has already reduced the crystal phase.

Common misconception20logN is always the reference-to-output scaling, regardless of R, D and mask plane.

Use N/(RD) from the original reference, N/D from the comparison input, and 1/D from the VCO output. Apply the relevant loop transfer after that plane mapping.

The frequency planner computes reduced rational numbers using arbitrary-precision integer products. Nearest rounding resolves an exact half-way tie toward the lower candidate. It never changes R, D or the requested frequency to disguise an off-grid result.

07 / 10

Fractional-N flexibility and fractional artifacts

A fractional synthesizer realizes a chosen average feedback ratio rather than requiring each divider cycle to have that ratio. In the teaching arithmetic, N=INT+FRAC/MOD. At the default, 61+1024/4096=61¼, so 40 MHz×61.25=2.450000 GHz.

\begin{aligned}K &= \operatorname{round}_{\mathrm{lower\_tie}}(x\cdot \mathrm{MOD}) \\ \mathrm{INT} &= \operatorname{floor}(\frac{K}{\mathrm{MOD}})\qquad \mathrm{FRAC} = K \text{mod} \mathrm{MOD} \\ \text{Quantum} &= \frac{f_{\mathrm{PFD}}}{\mathrm{MOD}\cdot D}\end{aligned}

Exact fractional-grid arithmetic, not a modulator simulation. x=fdesired·D/fPFD; round half-way toward lower K. Preserve programmed INT/FRAC/MOD separately from the reduced fraction.

With MOD=4096, the quantum is exactly 78125/8 Hz=9765.625 Hz. A 10 MHz target step contains exactly 1024 quanta. Carry is explicit: if rounding reaches the next whole ratio, INT increments and FRAC becomes zero. Integer mode preserves but disables the stored modulus.

Changing the sequence of instantaneous division can shape quantization noise toward other offsets. Practical fractional architectures can also generate fractional, integer-boundary and coupling spurs. Average ratio and modulus alone cannot determine their levels. This lesson models neither the bitstream nor those nonlinear mechanisms; all discrete amplitudes are labelled fixtures.

Think about itDoes the exact fractional grid guarantee a lower phase-noise integral or lower spurs than integer-N?

Answer

No. The reference plane, comparison rate, additive detector noise, loop shape, VCO, fractional sequence and hardware coupling all matter. Our synthetic fractional case fails a spur limit while the exact integer case passes the modeled gates. That is a fixture outcome, not a ranking of real topologies.

Five canonical frequency plans · exact rational arithmetic; all other controls at defaults, fc=100 kHz, ζ=0.70, 10 Hz–20 MHz, Illustrative masks
Target / mode / R	PFD / N / D	Actual / signed error	Quantum / step feasible	±20 ppm / original-reference scaling	Random ps / verdict
2.450000 GHz / fractional-N / R=1	40.000000 MHz / 61 + 1024/4096 / D=1	2.450000 GHz / 0.000000 Hz	9765.625000 Hz / yes	±49000.000000 Hz / 35.742122 dB	1.26185 / reject
2.450000 GHz / integer-N / R=8	5.000000 MHz / 490 + 0/1 / D=1	2.450000 GHz / 0.000000 Hz	5000000.000000 Hz / yes	±49000.000000 Hz / 35.742122 dB	1.26192 / model-pass against illustrative criteria
2.450000 GHz / integer-N / R=1	40.000000 MHz / 61 + 0/1 / D=1	2.440000 GHz / -10000000.000000 Hz	40000000.000000 Hz / no	±48800.000000 Hz / 35.706597 dB	1.26185 / reject
2.550000 GHz / fractional-N / R=1	40.000000 MHz / 63 + 3072/4096 / D=1	2.550000 GHz / 0.000000 Hz	9765.625000 Hz / yes	±51000.000000 Hz / 36.089604 dB	1.26183 / reject
2.550000 GHz / integer-N / R=8	5.000000 MHz / 510 + 0/1 / D=1	2.550000 GHz / 0.000000 Hz	5000000.000000 Hz / yes	±51000.000000 Hz / 36.089604 dB	1.26190 / model-pass against illustrative criteria

The final two rows preserve the distinct 04.6 handoff: 2.550000 GHz needs N=63+3072/4096 at R=1, or N=510 at R=8. They do not replace the approved 2.450000 GHz teaching case.

08 / 10

Loop bandwidth trades noise against settling

The loop follows slow reference-side phase changes and corrects slow VCO perturbations. At sufficiently high offset the VCO dominates its own phase because the loop cannot correct rapidly. Between those limits, damping and peaking matter. “Bandwidth” needs a definition before comparing two designs.

\begin{aligned}D(s) &= s^{2} + 2\zeta \omega _{n} s + \omega _{n}^{2} \\ H_{\mathrm{ref}}(s) &= \frac{2\zeta \omega _{n} s + \omega _{n}^{2}}{D(s)} \\ H_{\mathrm{vco}}(s) &= \frac{s^{2}}{D(s)} = 1-H_{\mathrm{ref}}(s)\end{aligned}

p04-m07-pll-noise-v1: normalized continuous second-order type-II model. s=j2πfoffset [rad/s]; ζ dimensionless, ωn [rad/s]. D(s) below is a polynomial, distinct from output-divider D.

\begin{aligned}\frac{\omega _{c}}{\omega _{n}} &= \sqrt{2\zeta ^{2} + \sqrt{4\zeta ^{4}+1}} \\ \frac{\omega _{c}}{\omega _{n}} &= 1.542771159\qquad f_{n} = 64.818427 \mathrm{kHz}\end{aligned}

UI fc is OPEN-LOOP unity-gain crossover, not a closed-loop −3 dB bandwidth. ωc=2πfc; fn=ωn/(2π). Default fc=100.000 kHz, ζ=0.700.

Go deeperDerive the crossover mapping and check the limits

The corresponding normalized open loop is G(s)=(2ζωns+ωn²)/s². Setting |G(jωc)|²=1 gives x⁴−4ζ²x²−1=0 for x=ωc/ωn. Its positive root is the ratio above. At DC, Href=1 and Hvco=0; at high offset, Href→0 and Hvco→1. Their complex sum is one, but their squared magnitudes do not generally sum to one: independent noise powers do not interfere coherently.

The retained Href numerator zero also matters for the step response. It differs from a simplified all-pole second-order approximation. The analytic branches below are derived from this exact teaching kernel; a textbook “lock-time” formula with another numerator is not substituted.

Output-density mapping · dBc/Hz after plane scaling and loop shaping, before LINEAR summation; Illustrative masks only
Contributor	Mapping to final output
Original reference	Lref,table +20log₁₀(factual/fref)+10log₁₀\|Href\|²
Stored PFD / divider / charge-pump proxy	Lpfd,table +20log₁₀[(N/D)/61.25]+10log₁₀\|Href\|²
VCO output	Lvco,table −20log₁₀D+10log₁₀\|Hvco\|²
Final buffer	−165 dBc/Hz, unshaped
Total	10log₁₀[Σ 10^(Li,out/10)]; contributors assumed uncorrelated

The exact 2.450 GHz integer plan shifts the stored PFD proxy up 18.061800 dB relative to the fractional plan. At 2.550 GHz the proxy adjustments are +0.347482 dB for R=1 and +18.409282 dB for R=8. This is the frozen input-equivalent proxy assumption, not a measured device figure of merit. Two independent −100 dBc/Hz contributors sum to −96.989700 dBc/Hz, never −200 dBc/Hz.

Original reference
PFD proxy
VCO
Output buffer
Total

Selected marker: 10 Hz, total -44.257878 dBc/Hz; dominant Original reference. Full-span curve; changing integration bounds changes its integral, not the underlying density.

Illustrative · final ideal divided-output plane · carrier 2.450000 GHz · positive-offset one-sided SSB dBc/Hz, 1 Hz normalization · 10–20000000 Hz random integration, discrete spurs excluded. p04-m07-pll-noise-v1; canonical-2p4-v1. No real LO-load or device-noise qualification.

One-sided random density area: 1.886596178e-4
Random RMS phase / time: 0.019424707 rad / 1.26185 ps
Random RMS phase, degrees: 1.112954°
Exact clipped-grid nodes: 4097 · twice the area is phase variance

Output-referred key densities · dBc/Hz, SSB 1 Hz; e^(+jωt), Illustrative, discrete spurs excluded
Offset Hz	Reference	PFD proxy	VCO	Buffer	Total / dominant
10	-44.257878	-130.000000	-187.467940	-165.000000	-44.257878 / Original reference
100	-74.257857	-134.999979	-177.467939	-165.000000	-74.257854 / Original reference
1000	-99.255811	-139.997933	-162.467898	-165.000000	-99.255442 / Original reference
10000	-114.058185	-144.800307	-144.466265	-165.000000	-114.050543 / Original reference
100000	-119.901388	-150.643510	-125.643510	-165.000000	-118.872150 / Original reference
1000000	-143.091395	-175.833517	-139.999347	-165.000000	-138.255552 / VCO
10000000	-165.101247	-198.843369	-154.999993	-165.000000	-154.216379 / VCO
20000000	-171.121922	-204.864044	-157.999998	-165.000000	-157.036885 / VCO

Dominant-source boundaries on 4097 full-span log nodes · boundary interpolated versus log offset, not a device crossover measurement
Transition	Bracketing offsets (Hz)	Interpolated boundary (Hz)
Original reference → VCO	415038.971949–416511.710184	415926.831192

Integrated contributor areas · linear ratio over the selected offset bounds; not sums of dBc/Hz
Contributor	One-sided area
Original reference	1.885832668e-4
PFD proxy	3.002995636e-10
VCO	7.541826370e-8
Output buffer	6.324552158e-10

Dominance is chosen at 4097 full-span nodes. A relative tie within 10⁻¹² uses reference, PFD, VCO, buffer order. At a winner change, the old and new contributors’ dB difference is zero-interpolated against log offset; the bracket and identities remain in the evidence record. Peaking is separately sampled at 4097 points from f/fn=10⁻⁴ to 10⁴ and is descriptive.

A frequency-command step follows Href. With final-output command amplitude Δfcommand, normalized error has transform E(s)=s/D(s); absolute error is Δfcommand×e(t). Command amplitude rescales the plotted axis only. It never proves a physical loop stays within a small perturbation.

\begin{aligned}\zeta<1:\quad e(t)&=e^{-at}\left[\cos(\omega_d t)-\frac{a}{\omega_d}\sin(\omega_d t)\right]\\\zeta=1:\quad e(t)&=e^{-\omega_n t}(1-\omega_n t)\\\zeta>1:\quad e(t)&=\frac{-p_1e^{-p_1t}+p_2e^{-p_2t}}{p_2-p_1}\end{aligned}

Exact inverse transforms of E(s)=s/D(s). t [s]; a=ζωn; ωd=ωn√(1−ζ²); overdamped p1,2=ωn(ζ∓√(ζ²−1)) are positive.

Selected time 11.987174 µs: normalized error -0.020000000, absolute error -19999.999748 Hz for a 1000000 Hz command. Amplitude rescales this axis only. First-and-stay 11.987174 µs; not lock time, acquisition, or a guarantee of small-signal operation.

Linear loop evidence · normalized type-II second order; fc is open-loop unity-gain crossover
Quantity	Value / validity
ωc/ωn; natural frequency	1.542771159; 64.818427 kHz
Href sampled peak	2.120024 dB at 51071.999782 Hz
Hvco sampled peak	0.001738 dB at 458466.770325 Hz
Peaking grid	4097 log nodes, f/fn=10⁻⁴…10⁴; lower-frequency exact tie; descriptive, not a gate
Linear 2% first-and-stay	11.987174 µs; final entering crossing of \|e\|≤0.02
Dominant-exponential approximation	13.722240 µs; −ln(0.02)/(ζωn), not exact envelope
Conservative underdamped envelope	14.903188 µs; exp(−ζωnt)/√(1−ζ²)
Horizon and tail proof	70.154187 µs; bound 2.886192368e-9 <0.02; 65537 uniform samples

Step trace key points · linear output-frequency error, command amplitude does not set normalized settling
Time (µs)	Normalized e(t)	Absolute error (Hz)
0.000000	1.000000000	1000000.000000
5.993587	-0.205954914	-205954.914167
11.987174	-0.020000000	-19999.999748
23.974349	0.000158974	158.973996
70.154187	-0.000000002	-0.001987

Go deeperFirst-and-stay, an exponential estimate and a conservative envelope

The continuous target is the earliest t after which |e(τ)|≤0.02 for every later τ. The numerical estimate samples 65537 uniform points to 20/pslow, where pslow is ζωn below critical damping, ωn at critical damping, and p1 above it. Linearly interpolate every entering crossing and retain the last.

The monotone horizon bound is exp(−at)/√(1−ζ²) below critical damping, exp(−ωnt)(1+ωnt) at critical damping, or [p1exp(−p1t)+p2exp(−p2t)]/(p2−p1) above it. A bound below 0.02 proves no later tail exit; otherwise return inspect. The default last crossing is 11.987174 µs. The dominant exponential estimate 13.722240 µs omits the underdamped envelope factor; the conservative envelope crossing is 14.903188 µs. Neither replaces the sampled estimate.

Fixed comparison · 2.450000 GHz fractional R=1, N=61.25, D=1; ζ=0.700, canonical-2p4-v1, SSB 1 Hz, 10 Hz–20 MHz, random only
Crossover (kHz)	RMS phase (rad)	Random RMS time (ps)	Linear 2% first-and-stay (µs)
10.000000	0.019420643	1.26159	119.871745
100.000000	0.019424707	1.26185	11.987174
400.000000	0.019447164	1.26331	2.996794

Common misconceptionLower bandwidth is always quieter; wider bandwidth gives free speed.

Bandwidth moves the contribution balance and may expose peaking or more reference-side noise. With these particular masks, 10/100/400 kHz barely change integrated jitter while changing the linear time scale strongly. Different masks or bounds can reverse the noise trend. The local fc≤0.10fPFD criterion screens this teaching model; it is not a universal design rule.

Model, masks, planes and numerical contract

kernel: p04-m07-pll-noise-v1
allocator: p04-m07-pll-allocator-v1
decision: p04-m07-decision-v1
masks: canonical-2p4-v1
reference: p04-m07-ref-mask-v1
pfd: p04-m07-pfd-mask-v1
vco: p04-m07-vco-mask-v1
spurs: p04-m07-paired-spurs-v1
evidence: Illustrative / Simulated; never measured
convention: e^(+jωt); positive-offset one-sided SSB L in dBc/Hz, normalized to 1 Hz; Sφ,one-sided=2Llinear; Sφ,two-sided=Llinear
plane: Final ideal divided output, before any real LO-load interface
validity: Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.
interpolation: dB linear versus log10(offset), 10 Hz–20 MHz, no extrapolation; flat across the valid nominal carrier range
integration: 4097 log nodes: 10×2000000^(i/4096) Hz; forced endpoints; inserted exact bounds once, interior nodes retained; ordinary-Hz trapezoids; 8193-node independent convergence <2e-5 relative
loop: Normalized continuous second-order type-II, fc is open-loop unity-gain crossover; no sampled-data or physical loop-filter synthesis
settling: 65537 uniform samples to 20/pslow; final entering 2% crossing linearly interpolated; monotone tail bound <0.02 required
dominance: 4097 full-span nodes; relative ties ≤1e-12 prefer reference, PFD proxy, VCO, buffer; changed-winner dB zero interpolated versus log offset
precision: Internals unrounded; displays half away from zero: MHz/GHz/dB/µs 6 decimals, ps 5 decimals
source: Local frozen builder tables, independent Python oracle; theory: Banerjee 5th ed. SNAA106C (2017), ADI MT-008 Rev. A (2008)

Current actual carrier 2.450000 GHz. Stored PFD density is final-output-referred at (N/D)₀=61.25; its input-equivalent density is assumed invariant over the valid PFD interval. Output buffer is −165 dBc/Hz, unshaped. Full-precision values control all gates; display precision never does.

09 / 10

Spurs, supply coupling, layout, and lock detection

A narrow tone can come from reference/PFD activity, periodic fractional patterns, supply ripple, control-node coupling or leakage between blocks. The path through the circuit determines its frequency and amplitude. A clean-looking random-noise integral can coexist with an unacceptable discrete line.

All comparison spur fixtures · paired tones, dBc per side at final divided output; not predicted by MOD; limits apply at every listed offset
Pair / positive offset	dBc per side / limit	Plan / RMS applicability	Selection / gate
Fractional pair / 10.000000 MHz	-80.000000 / -68.000000	Applicable; Eligible for optional small-angle RMS	Not selected; pass
Fractional / reference-PFD pair / 40.000000 MHz	-65.000000 / -68.000000	Applicable; Outside selected bounds; excluded from RMS	Not selected; reject
Exact-integer PFD pair / 5.000000 MHz	-70.000000 / -68.000000	Unavailable; Fixture unavailable for this plan	Not selected; inspect

Random-only: 1.26185 ps RMS

Optional selected-tone + random summary: 0.019424707 rad, 1.26185 ps RMS. Added selected-pair variance: 0.000000000e+0 rad². Only applicable selected pairs inside 10–20000000 Hz contribute. The 40 MHz pair remains outside these bounds and still enters the all-offset spur decision.

For Ls dBc per side: σφ,pair² = 2×10^(Ls/10). The −80 dBc pair alone contributes 2×10⁻⁸ rad². No dBc tone is integrated as dBc/Hz.

The fractional ±10/±40 MHz fixtures apply only to a mask-valid fractional plan with nonzero FRAC, R=D=1 and exactly 40 MHz PFD. The ±5 MHz fixture applies only to a mask-valid, zero-error integer plan at R=8, D=1 and exactly 5 MHz PFD. Other plans have no claimed spur amplitudes, including fractional mode with FRAC=0. They return inspect for missing spur evidence.

Common misconceptionDiscrete spurs are integrated exactly like random dBc/Hz density.

A paired line given as Ls dBc per side has small-angle variance 2×10^(Ls/10) rad². Add that variance only when explicitly requested and in bounds, and label the combined result separately. The all-offset spur gate still evaluates every applicable fixture, including the 40 MHz row outside this UI’s integration range.

Keysight’s E5055A documentation distinguishes spur omission and spur reporting. This lesson fixes its own explicit treatment; it does not assume an instrument’s default spur handling. Measurement procedures, residual instrument noise, calibration and uncertainty belong to Path 08.

Evidence-only sleep/wake and LO interface request · not scored by the analytic loop
Request	Distinguish / verify
Nominal 3.3 V; active synthesizer ≤75 mW	Define reference, PLL, VCO and buffer power boundaries and actual supply corners.
Sleep current ≤10 µA	Output-disabled and standby are different states; identify which oscillators remain on.
Wake to spectrally usable LO ≤1.000 ms	Reference startup → VCO calibration/nonlinear acquisition → lock indication → spectrum/drive readiness. They need separate evidence.
2.550000 GHz at +7.000 dBm into matched 50 Ω mixer LO port	Frequency arithmetic does not establish output power, loss, load pulling, return loss or spectral purity under that load.
All required temperatures and modes	Control-node ripple, supply pushing, coupling, load pulling and bias transients may change the spectrum.

Think about itCan the 11.987174 µs linear result be used to approve a 1 ms wake request?

Answer

No. It starts with a linearized operating loop and excludes reference startup, VCO calibration, saturation, cycle slips and real spectral readiness. A lock bit can assert before the required output conditions are established, or fail to distinguish an unsuitable state under its detector criterion.

Common misconceptionLock detect proves phase noise and spurs meet requirements.

The detector observes its configured comparison condition. It does not measure the mixer-port spectrum or power. Preserve the detector threshold, observation point and state sequence, then verify the actual requirement separately.

Go deeperThree real data sheets: keep the conditions, reject the headline shortcut

ADF4351 Rev. A gives a 0.27 ps typical example at RFOUT=2111.28 MHz, VCO=4222.56 MHz, REFIN=122.88 MHz, PFD=30.72 MHz, N=137 and D=2: R=4. Its 60 kHz loop, 2.5 mA charge pump, low-noise mode, 3.3 V/25 °C context and evaluation-board output matter. Figure 10 displays 1 kHz–10 MHz offsets; the cited jitter row does not establish complete integration/spur-omission bookkeeping. Request that before comparison. Neither the device’s modulus limit nor its VCO range equals this local model’s synthetic bounds.

HMC385LP4/LP4E v02.0705 is a separate free-running 2.25–2.5 GHz VCO example. At 3 V, 25 °C and Vtune=5 V, the RF-output SSB row gives −115 dBc/Hz at 100 kHz offset. The table does not tie that tuning voltage to an exact carrier in the row; no bounded jitter follows from one point. Typical output is +4.5 dBm and current 35 mA; pulling is specified into 2:1 VSWR, and pushing separately in MHz/V. No R/PFD/N loop applies to this free-running row. It neither covers the 2.550 GHz handoff nor establishes +7 dBm delivered drive.

SiT8208 Rev. 1.02, 24 June 2013 is a MEMS reference-oscillator comparison, not our crystal mask. Its random phase-jitter row is at 10 MHz over 12 kHz–20 MHz with a 15 pF logic-output load, not a 40 MHz RF port. At 3.3 V the standby limit is 70 µA; startup and standby-resume limits are 10 ms, distinct from output-enable timing. Stability options include initial tolerance, temperature, supply and load variation, while aging is separate. Industrial temperature is −40…+85 °C. Require exact ordering option, 40 MHz spectrum, spur treatment and operating state before reuse.

These official documents were rechecked 6 September 2026. They illustrate evidence discipline; none supplies a curve or coefficient to the allocator. ADI’s design/debug article also identifies internal observation points and the control node as useful evidence, without equating lock status to a clean LO.

The definitions are now in place. Commit a plan below, read every gate, and decide which result deserves a hardware evidence request.

Apply the model · compare frequency plans

PLL Noise & Settling Allocator

Choose a frequency plan and a bandwidth region. Keep the original reference, comparison input, VCO and final output planes separate, then name the evidence still missing.

p04-m07-pll-allocator-v1 · kernel p04-m07-pll-noise-v1

Try integer R=1: identify the frequency error and 10 MHz step failure.
Compare fractional R=1 with exact integer R=8. Explain why crystal-plane scaling stays the same.
Apply 10, 100 and 400 kHz bandwidths: inspect contributor transitions and linear settling.
Raise the lower integration bound: explain why jitter changes while ±ppm does not.
Keep the all-offset spur limit separate. Then enter 2550000000 Hz and allocate the 04.6 LO, carrying +7 dBm, supply and wake evidence forward.

1 · Exact frequency plan

Frequency-plan presetPresets atomically restore reference, target, R, D, mode and MOD. Other controls retain your values.

Divider modeInteger mode preserves MOD without using it.

Original reference (Hz)1000000–200000000; step 1.

Desired final output (Hz)100000000–10000000000; step 1.

R divider (integer)1–128; step 1.

Output divider DDivides VCO frequency and ideally reduces its phase-noise density by 20log₁₀D dB.

Programmed modulus MOD (integer)2–1048576; step 1. Preserved while integer mode disables its use.

Reference tolerance magnitude (ppm)0–100; step 1. Displayed as ± magnitude, separately from programmed error.

Target channel step (origin untested) (Hz)1–100000000; step 1.

Maximum allowed PFD (Hz)1000000–200000000; step 1.

2 · Loop and bounded random noise

Mask presetExactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.

Loop unity-gain crossover (Hz)100–5000000; step 1. fc≤0.10 fPFD is a local teaching screen.

Damping ζ (dimensionless)0.3–2; step 0.01.

Integration lower offset (Hz)10–19999999; step 1.

Integration upper offset (Hz)11–20000000; step 1.

Displayed frequency-command step (Hz)1–10000000; step 1. Rescales absolute error only; never proves physical small-signal operation.

3 · Local illustrative decision criteria

Maximum absolute programmed error (Hz)0–100000000; step 1.

Maximum random RMS time jitter (ps)0.1–100; step 0.1.

Maximum discrete spur, per side (dBc)-120–-40; step 1.

Maximum linear 2% first-and-stay (µs)1–100000; step 1.

4 · Optional small-angle RMS inclusion, committed plan

Random-only remains visible. All rows remain in the comparison table. Apply a changed frequency plan first to refresh eligibility; then select applicable in-bound pairs and apply.

Include ±10 MHz, -80 dBc/side in small-angle RMS

Eligible for optional small-angle RMS

Include ±40 MHz, -65 dBc/side in small-angle RMS

Outside selected bounds; excluded from RMS

Include ±5 MHz, -70 dBc/side in small-angle RMS

Fixture unavailable for this plan

Results match committed inputs.

Default fractional plan: exact carrier and channel step; reject on the −65 dBc/side 40 MHz fixture. Hardware evidence remains required.

JavaScript is off. The complete default result, canonical comparison plans, tables, recommendation and printable capstone remain available. Controls require JavaScript.

Actual divided output: 2.450000 GHz
Signed programmed error: 0.000000 Hz
Reference → PFD → VCO: 40.000000 MHz → 40.000000 MHz → 2.450000 GHz
R / programmed N / D: 1 / 61 + 1024/4096 / 1
Preserved MOD / reduced fractional part: 4096 / 1/4
Channel quantum / exact target multiple: 9765.625000 Hz (78125/8) / 1024/1
Reference-tolerance excursion, ±20 ppm: ±49000.000000 Hz
Original reference / PFD / VCO scaling to output: 35.742122 / 35.742122 / 0.000000 dB
Stored canonical PFD-proxy adjustment: 0.000000 dB
Crossover fc / natural fn / damping ζ: 100.000000 / 64.818427 kHz / 0.70

Step feasibility tests the channel spacing only; no channel-grid origin is specified. ±ppm excursion and signed programmed error are separate quantities.

Bracketing integer candidates for the current desired output · not automatic retuning
Integer N	Final output (GHz)	Signed error (Hz)
61	2.440000	-10000000.000000
62	2.480000	30000000.000000

Model verdict: reject

Against p04-m07-decision-v1. Each gate below is independent. Hardware inspection remains required even when every modeled criterion passes.

Independent local decision gates · Illustrative criteria, no wireless-standard or compliance claim
Gate	State	Result and binding condition
Programmed frequency error	pass	0.000000 Hz signed; magnitude ≤1000 Hz. Reference tolerance is separate.
Target-step divisibility	pass	1024/1 quanta per target step; must be a positive integer. Origin untested.
PFD maximum	pass	40.000000 MHz ≤100.000000 MHz.
N / VCO domain	pass	16≤N≤65535; 2.000000≤fVCO≤10.000000 GHz. N=245/4; VCO=2.450000 GHz.
Local crossover / PFD	pass	100000 Hz ≤0.10×fPFD; educational criterion, not a universal law.
Mask validity	pass	Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.
Random jitter	pass	1.26185 ps ≤2.0 ps; 10–20000000 Hz, random only.
Spur ±10 MHz	pass	-80 dBc/side ≤-68 dBc/side; all-offset decision independent of integration bounds.
Spur ±40 MHz	reject	-65 dBc/side ≤-68 dBc/side; all-offset decision independent of integration bounds.
Linear 2% first-and-stay	pass	11.987174 µs ≤20.000000 µs; not nonlinear acquisition or wake time.

Hardware inspect · evidence required

Evidence required: nominal 3.3 V supply; active synthesizer power ≤75 mW at actual operating conditions.
Evidence required: sleep current ≤10 µA; define which reference and output buffers remain powered.
Evidence required: wake request to spectrally usable LO ≤1.000 ms, including reference startup, nonlinear acquisition and spectral settling.
Evidence required: 2.550000 GHz, +7.000 dBm delivered to the matched 50 Ω 04.6 mixer LO port; qualify buffer, loss, mismatch, pulling and drive at that plane.
Evidence required: temperature, supply corners, real lock indication, output-load sensitivity, supply/control coupling and spurs in every operating mode.

Inspect a key phase-noise offset (Hz)

Original reference
PFD proxy
VCO
Output buffer
Total

Selected marker: 10 Hz, total -44.257878 dBc/Hz; dominant Original reference. Full-span curve; changing integration bounds changes its integral, not the underlying density.

One-sided random density area: 1.886596178e-4
Random RMS phase / time: 0.019424707 rad / 1.26185 ps
Random RMS phase, degrees: 1.112954°
Exact clipped-grid nodes: 4097 · twice the area is phase variance

Output-referred key densities · dBc/Hz, SSB 1 Hz; e^(+jωt), Illustrative, discrete spurs excluded
Offset Hz	Reference	PFD proxy	VCO	Buffer	Total / dominant
10	-44.257878	-130.000000	-187.467940	-165.000000	-44.257878 / Original reference
100	-74.257857	-134.999979	-177.467939	-165.000000	-74.257854 / Original reference
1000	-99.255811	-139.997933	-162.467898	-165.000000	-99.255442 / Original reference
10000	-114.058185	-144.800307	-144.466265	-165.000000	-114.050543 / Original reference
100000	-119.901388	-150.643510	-125.643510	-165.000000	-118.872150 / Original reference
1000000	-143.091395	-175.833517	-139.999347	-165.000000	-138.255552 / VCO
10000000	-165.101247	-198.843369	-154.999993	-165.000000	-154.216379 / VCO
20000000	-171.121922	-204.864044	-157.999998	-165.000000	-157.036885 / VCO

Dominant-source boundaries on 4097 full-span log nodes · boundary interpolated versus log offset, not a device crossover measurement
Transition	Bracketing offsets (Hz)	Interpolated boundary (Hz)
Original reference → VCO	415038.971949–416511.710184	415926.831192

Integrated contributor areas · linear ratio over the selected offset bounds; not sums of dBc/Hz
Contributor	One-sided area
Original reference	1.885832668e-4
PFD proxy	3.002995636e-10
VCO	7.541826370e-8
Output buffer	6.324552158e-10

All comparison spur fixtures · paired tones, dBc per side at final divided output; not predicted by MOD; limits apply at every listed offset
Pair / positive offset	dBc per side / limit	Plan / RMS applicability	Selection / gate
Fractional pair / 10.000000 MHz	-80.000000 / -68.000000	Applicable; Eligible for optional small-angle RMS	Not selected; pass
Fractional / reference-PFD pair / 40.000000 MHz	-65.000000 / -68.000000	Applicable; Outside selected bounds; excluded from RMS	Not selected; reject
Exact-integer PFD pair / 5.000000 MHz	-70.000000 / -68.000000	Unavailable; Fixture unavailable for this plan	Not selected; inspect

Random-only: 1.26185 ps RMS

For Ls dBc per side: σφ,pair² = 2×10^(Ls/10). The −80 dBc pair alone contributes 2×10⁻⁸ rad². No dBc tone is integrated as dBc/Hz.

Inspect a linear step key point

Linear loop evidence · normalized type-II second order; fc is open-loop unity-gain crossover
Quantity	Value / validity
ωc/ωn; natural frequency	1.542771159; 64.818427 kHz
Href sampled peak	2.120024 dB at 51071.999782 Hz
Hvco sampled peak	0.001738 dB at 458466.770325 Hz
Peaking grid	4097 log nodes, f/fn=10⁻⁴…10⁴; lower-frequency exact tie; descriptive, not a gate
Linear 2% first-and-stay	11.987174 µs; final entering crossing of \|e\|≤0.02
Dominant-exponential approximation	13.722240 µs; −ln(0.02)/(ζωn), not exact envelope
Conservative underdamped envelope	14.903188 µs; exp(−ζωnt)/√(1−ζ²)
Horizon and tail proof	70.154187 µs; bound 2.886192368e-9 <0.02; 65537 uniform samples

Step trace key points · linear output-frequency error, command amplitude does not set normalized settling
Time (µs)	Normalized e(t)	Absolute error (Hz)
0.000000	1.000000000	1000000.000000
5.993587	-0.205954914	-205954.914167
11.987174	-0.020000000	-19999.999748
23.974349	0.000158974	158.973996
70.154187	-0.000000002	-0.001987

Fixed 10 / 100 / 400 kHz reference comparisons

These reference rows always retain the canonical fractional plan, masks, bounds and criteria; they are not recalculated from custom controls.

Fixed comparison · 2.450000 GHz fractional R=1, N=61.25, D=1; ζ=0.700, canonical-2p4-v1, SSB 1 Hz, 10 Hz–20 MHz, random only
Crossover (kHz)	RMS phase (rad)	Random RMS time (ps)	Linear 2% first-and-stay (µs)
10.000000	0.019420643	1.26159	119.871745
100.000000	0.019424707	1.26185	11.987174
400.000000	0.019447164	1.26331	2.996794

Model, masks, planes and numerical contract

kernel: p04-m07-pll-noise-v1
allocator: p04-m07-pll-allocator-v1
decision: p04-m07-decision-v1
masks: canonical-2p4-v1
reference: p04-m07-ref-mask-v1
pfd: p04-m07-pfd-mask-v1
vco: p04-m07-vco-mask-v1
spurs: p04-m07-paired-spurs-v1
evidence: Illustrative / Simulated; never measured
convention: e^(+jωt); positive-offset one-sided SSB L in dBc/Hz, normalized to 1 Hz; Sφ,one-sided=2Llinear; Sφ,two-sided=Llinear
plane: Final ideal divided output, before any real LO-load interface
validity: Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.
interpolation: dB linear versus log10(offset), 10 Hz–20 MHz, no extrapolation; flat across the valid nominal carrier range
integration: 4097 log nodes: 10×2000000^(i/4096) Hz; forced endpoints; inserted exact bounds once, interior nodes retained; ordinary-Hz trapezoids; 8193-node independent convergence <2e-5 relative
loop: Normalized continuous second-order type-II, fc is open-loop unity-gain crossover; no sampled-data or physical loop-filter synthesis
settling: 65537 uniform samples to 20/pslow; final entering 2% crossing linearly interpolated; monotone tail bound <0.02 required
dominance: 4097 full-span nodes; relative ties ≤1e-12 prefer reference, PFD proxy, VCO, buffer; changed-winner dB zero interpolated versus log offset
precision: Internals unrounded; displays half away from zero: MHz/GHz/dB/µs 6 decimals, ps 5 decimals
source: Local frozen builder tables, independent Python oracle; theory: Banerjee 5th ed. SNAA106C (2017), ADI MT-008 Rev. A (2008)

Printable synthesizer evidence record · applied plan

Synthesizer evidence card · Illustrative / Simulated, not measured; actual committed values
Record field	Allocation / evidence boundary
Function and mode	Node/gateway LO, fractional-N; reject; p04-m07-decision-v1
Exact nominal frequency planes	Reference 40000000/1 Hz; PFD 40000000/1 Hz; VCO 2450000000/1 Hz; final output 2450000000/1 Hz.
Dividers	R=1, N=245/4, D=1, INT=61, FRAC=1024, stored MOD=4096.
Target, grid and deterministic accuracy	Target 2450000000 Hz; signed error 0/1 Hz; quantum 78125/8 Hz; requested step 10000000 Hz, feasible (origin untested). ±20 ppm gives ±49000.000000 Hz, separate from programmed error.
Masks / injection planes	canonical-2p4-v1; p04-m07-ref-mask-v1, p04-m07-pfd-mask-v1, p04-m07-vco-mask-v1; original reference / PFD comparison / VCO / ideal divided-output buffer. Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.
Plane scaling	Original reference 35.742122 dB; PFD input 35.742122 dB; stored PFD adjustment 0.000000 dB; VCO division 0.000000 dB.
Random-noise record	10–20000000 Hz; e^(+jωt); positive-offset one-sided SSB L in dBc/Hz, normalized to 1 Hz; Sφ,one-sided=2Llinear; Sφ,two-sided=Llinear. Area 1.886596178e-4, RMS 0.019424707 rad / 1.26185 ps; 4097 clipped nodes. No discrete spurs.
Discrete / optional combined	p04-m07-paired-spurs-v1; 10000000 Hz: -80 dBc/side, applicable, RMS excluded; 40000000 Hz: -65 dBc/side, applicable, RMS excluded; 5000000 Hz: -70 dBc/side, unavailable, RMS excluded. Optional combined 1.26185 ps, pair variance 0.000000000e+0 rad².
Loop / linear settling	p04-m07-pll-noise-v1; p04-m07-pll-allocator-v1; fc=100000 Hz, fn=64818.427153 Hz, ζ=0.7; command 1000000 Hz. Linear 2% first-and-stay 11.987174 µs. 65537 uniform samples to 20/pslow; final entering 2% crossing linearly interpolated; monotone tail bound <0.02 required Not nonlinear acquisition or wake time.
Local limits	Error ≤1000 Hz; random jitter ≤2 ps; every applicable spur ≤-68 dBc/side; linear first-and-stay ≤20 µs; PFD ≤100000000 Hz; fc≤0.10fPFD. Programmed frequency error: pass; Target-step divisibility: pass; PFD maximum: pass; N / VCO domain: pass; Local crossover / PFD: pass; Mask validity: pass; Random jitter: pass; Spur ±10 MHz: pass; Spur ±40 MHz: reject; Linear 2% first-and-stay: pass.
Supply, current, power, temperature and LO load	Evidence required: nominal 3.3 V; ≤75 mW active, ≤10 µA sleep; ≤1 ms wake to spectrally usable LO; 2.550 GHz/+7 dBm delivered into matched 50 Ω 04.6 mixer LO port. Nominal 25 °C analytic fixture; hardware temperature and supply corners unqualified.
Discriminating evidence request	Obtain condition-matched reference/PFD/VCO/buffer masks and all-offset per-side spurs at the actual carrier and planes. Verify loaded LO drive, pulling, supply/control coupling, current and temperature corners. Measure reference startup plus nonlinear acquisition and spectral readiness; compare with lock observation. Access date 2026-09-06; no device data fitted.

Copy the full machine-readable record with the allocator’s copy button, or select the text below. The evidence card above is retained in print.

{
  "function": "Node/gateway LO allocation; Class 1 Learn model",
  "ok": true,
  "input": {
    "refHz": 40000000,
    "tolerancePpm": 20,
    "r": 1,
    "desiredHz": 2450000000,
    "d": 1,
    "mode": "fractional-N",
    "mod": 4096,
    "stepHz": 10000000,
    "maxPfdHz": 100000000,
    "mask": "canonical-2p4-v1",
    "fcHz": 100000,
    "zeta": 0.7,
    "lowerHz": 10,
    "upperHz": 20000000,
    "commandHz": 1000000,
    "selectedSpurs": [],
    "maxErrorHz": 1000,
    "maxJitterPs": 2,
    "maxSpurDbc": -68,
    "maxSettlingUs": 20
  },
  "plan": {
    "reference": {
      "n": "40000000",
      "d": "1"
    },
    "pfd": {
      "n": "40000000",
      "d": "1"
    },
    "ideal": {
      "n": "245",
      "d": "4"
    },
    "n": {
      "n": "245",
      "d": "4"
    },
    "int": 61,
    "frac": 1024,
    "mod": 4096,
    "reducedFraction": {
      "n": "1",
      "d": "4"
    },
    "vco": {
      "n": "2450000000",
      "d": "1"
    },
    "actual": {
      "n": "2450000000",
      "d": "1"
    },
    "error": {
      "n": "0",
      "d": "1"
    },
    "quantum": {
      "n": "78125",
      "d": "8"
    },
    "stepMultiple": {
      "n": "1024",
      "d": "1"
    },
    "raster": true,
    "tolerance": {
      "n": "49000",
      "d": "1"
    },
    "brackets": [
      {
        "n": "61",
        "frequency": {
          "n": "2440000000",
          "d": "1"
        },
        "error": {
          "n": "-10000000",
          "d": "1"
        }
      },
      {
        "n": "62",
        "frequency": {
          "n": "2480000000",
          "d": "1"
        },
        "error": {
          "n": "30000000",
          "d": "1"
        }
      }
    ],
    "scaling": {
      "reference": 35.7421218607314,
      "pfd": 35.7421218607314,
      "pfdProxy": 0,
      "vco": 0
    }
  },
  "gates": [
    {
      "name": "Programmed frequency error",
      "state": "pass",
      "reason": "0.000000 Hz signed; magnitude ≤1000 Hz. Reference tolerance is separate."
    },
    {
      "name": "Target-step divisibility",
      "state": "pass",
      "reason": "1024/1 quanta per target step; must be a positive integer. Origin untested."
    },
    {
      "name": "PFD maximum",
      "state": "pass",
      "reason": "40.000000 MHz ≤100.000000 MHz."
    },
    {
      "name": "N / VCO domain",
      "state": "pass",
      "reason": "16≤N≤65535; 2.000000≤fVCO≤10.000000 GHz. N=245/4; VCO=2.450000 GHz."
    },
    {
      "name": "Local crossover / PFD",
      "state": "pass",
      "reason": "100000 Hz ≤0.10×fPFD; educational criterion, not a universal law."
    },
    {
      "name": "Mask validity",
      "state": "pass",
      "reason": "Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup."
    },
    {
      "name": "Random jitter",
      "state": "pass",
      "reason": "1.26185 ps ≤2.0 ps; 10–20000000 Hz, random only."
    },
    {
      "name": "Spur ±10 MHz",
      "state": "pass",
      "reason": "-80 dBc/side ≤-68 dBc/side; all-offset decision independent of integration bounds."
    },
    {
      "name": "Spur ±40 MHz",
      "state": "reject",
      "reason": "-65 dBc/side ≤-68 dBc/side; all-offset decision independent of integration bounds."
    },
    {
      "name": "Linear 2% first-and-stay",
      "state": "pass",
      "reason": "11.987174 µs ≤20.000000 µs; not nonlinear acquisition or wake time."
    }
  ],
  "verdict": "reject",
  "validMask": true,
  "random": {
    "area": 0.00018865961780254766,
    "areaBy": {
      "reference": 0.00018858326678407165,
      "pfd": 3.0029956358209545e-10,
      "vco": 7.541826369661469e-8,
      "buffer": 6.324552158059099e-10
    },
    "phaseRad": 0.019424706834469736,
    "phaseDegrees": 1.1129537198940413,
    "timePs": 1.2618522901292983,
    "nodes": 4097
  },
  "combined": {
    "spurVariance": 0,
    "phaseRad": 0.019424706834469736,
    "timePs": 1.2618522901292983
  },
  "spurs": [
    {
      "id": "frac-10",
      "offset": 10000000,
      "dbc": -80,
      "name": "Fractional pair",
      "applicable": true,
      "inside": true,
      "selected": false,
      "included": false,
      "passes": true,
      "reason": "Eligible for optional small-angle RMS"
    },
    {
      "id": "frac-40",
      "offset": 40000000,
      "dbc": -65,
      "name": "Fractional / reference-PFD pair",
      "applicable": true,
      "inside": false,
      "selected": false,
      "included": false,
      "passes": false,
      "reason": "Outside selected bounds; excluded from RMS"
    },
    {
      "id": "int-5",
      "offset": 5000000,
      "dbc": -70,
      "name": "Exact-integer PFD pair",
      "applicable": false,
      "inside": true,
      "selected": false,
      "included": false,
      "passes": true,
      "reason": "Fixture unavailable for this plan"
    }
  ],
  "loop": {
    "ratio": 1.5427711592634117,
    "fn": 64818.427152698714,
    "wn": 407266.1891203269,
    "peaks": {
      "ref": {
        "f": 51071.99978186911,
        "power": 1.629304852807925
      },
      "vco": {
        "f": 458466.77032535936,
        "power": 1.0004001599327754
      },
      "nodes": 4097,
      "normalizedRange": "1e-4…1e4 × fn"
    }
  },
  "keyRows": [
    {
      "f": 10,
      "linear": {
        "reference": 0.00003751562678585091,
        "pfd": 1.0000000476028565e-13,
        "vco": 1.7914555898951567e-19,
        "buffer": 3.1622776601683796e-17
      },
      "total": 0.00003751562688588272,
      "dominant": "reference"
    },
    {
      "f": 100,
      "linear": {
        "reference": 3.751580358489766e-8,
        "pfd": 3.1622927134970206e-14,
        "vco": 1.791455758736266e-18,
        "buffer": 3.1622776601683796e-17
      },
      "total": 3.751583524123903e-8,
      "dominant": "reference"
    },
    {
      "f": 1000,
      "linear": {
        "reference": 1.1869129022346712e-10,
        "pfd": 1.0004759764237745e-14,
        "vco": 5.665133600090322e-17,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.1870138325734397e-10,
      "dominant": "reference"
    },
    {
      "f": 10000,
      "linear": {
        "reference": 3.928090363205877e-12,
        "pfd": 3.3110770252897667e-15,
        "vco": 3.575802471627749e-15,
        "buffer": 3.1622776601683796e-17
      },
      "total": 3.935008865479397e-12,
      "dominant": "reference"
    },
    {
      "f": 100000,
      "linear": {
        "reference": 1.0229659392410907e-12,
        "pfd": 8.62281339248717e-16,
        "vco": 2.726773015886289e-13,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.2965371449455698e-12,
      "dominant": "reference"
    },
    {
      "f": 1000000,
      "linear": {
        "reference": 4.907502286538915e-15,
        "pfd": 2.6100469798796425e-18,
        "vco": 1.0001504277636225e-14,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.4943239387756703e-14,
      "dominant": "vco"
    },
    {
      "f": 10000000,
      "linear": {
        "reference": 3.0894080430157014e-17,
        "pfd": 1.305157991133078e-20,
        "vco": 3.162282969028633e-16,
        "buffer": 3.1622776601683796e-17
      },
      "total": 3.7875820551461543e-16,
      "dominant": "vco"
    },
    {
      "f": 20000000,
      "linear": {
        "reference": 7.723386217969338e-18,
        "pfd": 3.2628384145559535e-21,
        "vco": 1.5848938581680793e-16,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.9783881147487564e-16,
      "dominant": "vco"
    }
  ],
  "dominance": {
    "first": "reference",
    "boundaries": [
      {
        "from": "reference",
        "to": "vco",
        "lowerHz": 415038.9719485989,
        "upperHz": 416511.71018405264,
        "boundaryHz": 415926.83119209437
      }
    ]
  },
  "hardware": [
    "Evidence required: nominal 3.3 V supply; active synthesizer power ≤75 mW at actual operating conditions.",
    "Evidence required: sleep current ≤10 µA; define which reference and output buffers remain powered.",
    "Evidence required: wake request to spectrally usable LO ≤1.000 ms, including reference startup, nonlinear acquisition and spectral settling.",
    "Evidence required: 2.550000 GHz, +7.000 dBm delivered to the matched 50 Ω 04.6 mixer LO port; qualify buffer, loss, mismatch, pulling and drive at that plane.",
    "Evidence required: temperature, supply corners, real lock indication, output-load sensitivity, supply/control coupling and spurs in every operating mode."
  ],
  "meta": {
    "kernel": "p04-m07-pll-noise-v1",
    "allocator": "p04-m07-pll-allocator-v1",
    "decision": "p04-m07-decision-v1",
    "masks": "canonical-2p4-v1",
    "reference": "p04-m07-ref-mask-v1",
    "pfd": "p04-m07-pfd-mask-v1",
    "vco": "p04-m07-vco-mask-v1",
    "spurs": "p04-m07-paired-spurs-v1",
    "evidence": "Illustrative / Simulated; never measured",
    "convention": "e^(+jωt); positive-offset one-sided SSB L in dBc/Hz, normalized to 1 Hz; Sφ,one-sided=2Llinear; Sφ,two-sided=Llinear",
    "plane": "Final ideal divided output, before any real LO-load interface",
    "validity": "Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.",
    "interpolation": "dB linear versus log10(offset), 10 Hz–20 MHz, no extrapolation; flat across the valid nominal carrier range",
    "integration": "4097 log nodes: 10×2000000^(i/4096) Hz; forced endpoints; inserted exact bounds once, interior nodes retained; ordinary-Hz trapezoids; 8193-node independent convergence <2e-5 relative",
    "loop": "Normalized continuous second-order type-II, fc is open-loop unity-gain crossover; no sampled-data or physical loop-filter synthesis",
    "settling": "65537 uniform samples to 20/pslow; final entering 2% crossing linearly interpolated; monotone tail bound <0.02 required",
    "dominance": "4097 full-span nodes; relative ties ≤1e-12 prefer reference, PFD proxy, VCO, buffer; changed-winner dB zero interpolated versus log offset",
    "precision": "Internals unrounded; displays half away from zero: MHz/GHz/dB/µs 6 decimals, ps 5 decimals",
    "source": "Local frozen builder tables, independent Python oracle; theory: Banerjee 5th ed. SNAA106C (2017), ADI MT-008 Rev. A (2008)"
  },
  "settling": {
    "timeUs": 11.987174464897043,
    "horizon": 0.00007015418744468164,
    "tail": 2.886192367622901e-9,
    "crossings": [
      0.0000026307966859668614,
      0.000011987174464897043
    ],
    "samples": 65537,
    "dominantUs": 13.722239760535647,
    "envelopeUs": 14.903188260648689,
    "trace": [
      {
        "t": 0,
        "error": 1
      },
      {
        "t": 0.000008769273430585204,
        "error": -0.11299510413558037
      },
      {
        "t": 0.00001753854686117041,
        "error": 0.00866515868896817
      },
      {
        "t": 0.000026307820291755613,
        "error": -0.00041984973919866763
      },
      {
        "t": 0.00003507709372234082,
        "error": -0.000001152901149219045
      },
      {
        "t": 0.00004384636715292602,
        "error": 0.000002986084827301228
      },
      {
        "t": 0.00005261564058351123,
        "error": -3.9928467213503486e-7
      },
      {
        "t": 0.00006138491401409643,
        "error": 3.430903800952969e-8
      },
      {
        "t": 0.00007015418744468164,
        "error": -1.986531625132905e-9
      }
    ]
  },
  "hardwareRequest": {
    "supplyV": 3.3,
    "activePowerMaxMw": 75,
    "sleepCurrentMaxUa": 10,
    "wakeMaxMs": 1,
    "loHz": 2550000000,
    "deliveredDbm": 7,
    "loadOhm": 50,
    "temperature": "25 °C illustrative nominal; hardware temperature corners evidence required",
    "sourceStatus": "2026-09-06; synthetic masks, no device fit"
  },
  "verification": "Request condition-matched reference/PFD/VCO/buffer noise, per-side spurs at all relevant offsets, LO drive under real load, frequency corners, nonlinear wake and supply/current measurements."
}

10 / 10

Allocate the node and gateway synthesizer

For the 2.450000 GHz teaching case, carry forward exact integer R=8, fPFD=5 MHz, N=490, D=1 at 100 kHz crossover and ζ=0.700 as the provisional modeled choice. It represents the 10 MHz step, meets the 1 kHz programmed-error limit, gives 1.26192 ps random RMS jitter over 10 Hz–20 MHz, and has an applicable −70 dBc/side ±5 MHz fixture that passes −68 dBc/side. The 11.987174 µs linear estimate passes 20 µs. All supply/load/wake evidence remains required.

Reject R=1 integer at the same target because its −10 MHz programmed error and 40 MHz quantum fail. Reject the canonical fractional fixture because −65 dBc/side at ±40 MHz exceeds the spur limit even though its random 1.26185 ps and frequency arithmetic pass. A real fractional part can overturn this decision with condition-matched spur evidence; topology alone does not decide.

The fixed comparison suggests 100–400 kHz as a region worth further investigation for these illustrative masks: both meet 20 µs linear settling while 10 kHz does not. Use 100 kHz as the recorded nominal point. For the selected 5 MHz PFD this stays within the local 500 kHz screen. Reference noise dominates close to the carrier; the tabled crossover transfers dominance to the VCO farther out. Revisit this region with actual masks, spur limits, loop implementation and nonlinear transients.

For the 04.6 observation receiver, preserve 2.550000 GHz at +7.000 dBm delivered to the matched mixer LO port. The exact integer alternative is R=8, PFD=5 MHz, N=510, D=1, FRAC=0, with stored MOD=4096 inactive. The original-reference scaling is 36.089604 dB and ±20 ppm gives ±51.000 kHz. Random phase is 0.020218252 rad, area 2.043888645e-4, and random time jitter 1.26190 ps, SSB 1 Hz over 10 Hz–20 MHz at the ideal divided output. The fractional R=1 alternative uses 63+3072/4096 and gives 1.26183 ps, but retains its failing −65 dBc/side fixture.

Model verdict: model-pass against illustrative criteria

Against p04-m07-decision-v1. Each gate below is independent. Hardware inspection remains required even when every modeled criterion passes.

Independent local decision gates · Illustrative criteria, no wireless-standard or compliance claim
Gate	State	Result and binding condition
Programmed frequency error	pass	0.000000 Hz signed; magnitude ≤1000 Hz. Reference tolerance is separate.
Target-step divisibility	pass	2/1 quanta per target step; must be a positive integer. Origin untested.
PFD maximum	pass	5.000000 MHz ≤100.000000 MHz.
N / VCO domain	pass	16≤N≤65535; 2.000000≤fVCO≤10.000000 GHz. N=510/1; VCO=2.550000 GHz.
Local crossover / PFD	pass	100000 Hz ≤0.10×fPFD; educational criterion, not a universal law.
Mask validity	pass	Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.
Random jitter	pass	1.26190 ps ≤2.0 ps; 10–20000000 Hz, random only.
Spur ±5 MHz	pass	-70 dBc/side ≤-68 dBc/side; all-offset decision independent of integration bounds.
Linear 2% first-and-stay	pass	11.987174 µs ≤20.000000 µs; not nonlinear acquisition or wake time.

Hardware inspect · evidence required

Evidence required: nominal 3.3 V supply; active synthesizer power ≤75 mW at actual operating conditions.
Evidence required: sleep current ≤10 µA; define which reference and output buffers remain powered.
Evidence required: wake request to spectrally usable LO ≤1.000 ms, including reference startup, nonlinear acquisition and spectral settling.
Evidence required: 2.550000 GHz, +7.000 dBm delivered to the matched 50 Ω 04.6 mixer LO port; qualify buffer, loss, mismatch, pulling and drive at that plane.
Evidence required: temperature, supply corners, real lock indication, output-load sensitivity, supply/control coupling and spurs in every operating mode.

Printable synthesizer evidence record · applied plan

Synthesizer evidence card · Illustrative / Simulated, not measured; actual committed values
Record field	Allocation / evidence boundary
Function and mode	Node/gateway LO, integer-N; model-pass against illustrative criteria; p04-m07-decision-v1
Exact nominal frequency planes	Reference 40000000/1 Hz; PFD 5000000/1 Hz; VCO 2550000000/1 Hz; final output 2550000000/1 Hz.
Dividers	R=8, N=510/1, D=1, INT=510, FRAC=0, stored MOD=4096 (inactive).
Target, grid and deterministic accuracy	Target 2550000000 Hz; signed error 0/1 Hz; quantum 5000000/1 Hz; requested step 10000000 Hz, feasible (origin untested). ±20 ppm gives ±51000.000000 Hz, separate from programmed error.
Masks / injection planes	canonical-2p4-v1; p04-m07-ref-mask-v1, p04-m07-pfd-mask-v1, p04-m07-vco-mask-v1; original reference / PFD comparison / VCO / ideal divided-output buffer. Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.
Plane scaling	Original reference 36.089604 dB; PFD input 54.151404 dB; stored PFD adjustment 18.409282 dB; VCO division 0.000000 dB.
Random-noise record	10–20000000 Hz; e^(+jωt); positive-offset one-sided SSB L in dBc/Hz, normalized to 1 Hz; Sφ,one-sided=2Llinear; Sφ,two-sided=Llinear. Area 2.043888645e-4, RMS 0.020218252 rad / 1.26190 ps; 4097 clipped nodes. No discrete spurs.
Discrete / optional combined	p04-m07-paired-spurs-v1; 10000000 Hz: -80 dBc/side, unavailable, RMS excluded; 40000000 Hz: -65 dBc/side, unavailable, RMS excluded; 5000000 Hz: -70 dBc/side, applicable, RMS excluded. Optional combined 1.26190 ps, pair variance 0.000000000e+0 rad².
Loop / linear settling	p04-m07-pll-noise-v1; p04-m07-pll-allocator-v1; fc=100000 Hz, fn=64818.427153 Hz, ζ=0.7; command 1000000 Hz. Linear 2% first-and-stay 11.987174 µs. 65537 uniform samples to 20/pslow; final entering 2% crossing linearly interpolated; monotone tail bound <0.02 required Not nonlinear acquisition or wake time.
Local limits	Error ≤1000 Hz; random jitter ≤2 ps; every applicable spur ≤-68 dBc/side; linear first-and-stay ≤20 µs; PFD ≤100000000 Hz; fc≤0.10fPFD. Programmed frequency error: pass; Target-step divisibility: pass; PFD maximum: pass; N / VCO domain: pass; Local crossover / PFD: pass; Mask validity: pass; Random jitter: pass; Spur ±5 MHz: pass; Linear 2% first-and-stay: pass.
Supply, current, power, temperature and LO load	Evidence required: nominal 3.3 V; ≤75 mW active, ≤10 µA sleep; ≤1 ms wake to spectrally usable LO; 2.550 GHz/+7 dBm delivered into matched 50 Ω 04.6 mixer LO port. Nominal 25 °C analytic fixture; hardware temperature and supply corners unqualified.
Discriminating evidence request	Obtain condition-matched reference/PFD/VCO/buffer masks and all-offset per-side spurs at the actual carrier and planes. Verify loaded LO drive, pulling, supply/control coupling, current and temperature corners. Measure reference startup plus nonlinear acquisition and spectral readiness; compare with lock observation. Access date 2026-09-06; no device data fitted.

Copy the full machine-readable record with the allocator’s copy button, or select the text below. The evidence card above is retained in print.

{
  "function": "Node/gateway LO allocation; Class 1 Learn model",
  "ok": true,
  "input": {
    "refHz": 40000000,
    "tolerancePpm": 20,
    "r": 8,
    "desiredHz": 2550000000,
    "d": 1,
    "mode": "integer-N",
    "mod": 4096,
    "stepHz": 10000000,
    "maxPfdHz": 100000000,
    "mask": "canonical-2p4-v1",
    "fcHz": 100000,
    "zeta": 0.7,
    "lowerHz": 10,
    "upperHz": 20000000,
    "commandHz": 1000000,
    "selectedSpurs": [],
    "maxErrorHz": 1000,
    "maxJitterPs": 2,
    "maxSpurDbc": -68,
    "maxSettlingUs": 20
  },
  "plan": {
    "reference": {
      "n": "40000000",
      "d": "1"
    },
    "pfd": {
      "n": "5000000",
      "d": "1"
    },
    "ideal": {
      "n": "510",
      "d": "1"
    },
    "n": {
      "n": "510",
      "d": "1"
    },
    "int": 510,
    "frac": 0,
    "mod": 4096,
    "reducedFraction": {
      "n": "0",
      "d": "1"
    },
    "vco": {
      "n": "2550000000",
      "d": "1"
    },
    "actual": {
      "n": "2550000000",
      "d": "1"
    },
    "error": {
      "n": "0",
      "d": "1"
    },
    "quantum": {
      "n": "5000000",
      "d": "1"
    },
    "stepMultiple": {
      "n": "2",
      "d": "1"
    },
    "raster": true,
    "tolerance": {
      "n": "51000",
      "d": "1"
    },
    "brackets": [
      {
        "n": "510",
        "frequency": {
          "n": "2550000000",
          "d": "1"
        },
        "error": {
          "n": "0",
          "d": "1"
        }
      },
      {
        "n": "511",
        "frequency": {
          "n": "2555000000",
          "d": "1"
        },
        "error": {
          "n": "5000000",
          "d": "1"
        }
      }
    ],
    "scaling": {
      "reference": 36.08960378211985,
      "pfd": 54.15140352195873,
      "pfdProxy": 18.409281661227325,
      "vco": 0
    }
  },
  "gates": [
    {
      "name": "Programmed frequency error",
      "state": "pass",
      "reason": "0.000000 Hz signed; magnitude ≤1000 Hz. Reference tolerance is separate."
    },
    {
      "name": "Target-step divisibility",
      "state": "pass",
      "reason": "2/1 quanta per target step; must be a positive integer. Origin untested."
    },
    {
      "name": "PFD maximum",
      "state": "pass",
      "reason": "5.000000 MHz ≤100.000000 MHz."
    },
    {
      "name": "N / VCO domain",
      "state": "pass",
      "reason": "16≤N≤65535; 2.000000≤fVCO≤10.000000 GHz. N=510/1; VCO=2.550000 GHz."
    },
    {
      "name": "Local crossover / PFD",
      "state": "pass",
      "reason": "100000 Hz ≤0.10×fPFD; educational criterion, not a universal law."
    },
    {
      "name": "Mask validity",
      "state": "pass",
      "reason": "Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup."
    },
    {
      "name": "Random jitter",
      "state": "pass",
      "reason": "1.26190 ps ≤2.0 ps; 10–20000000 Hz, random only."
    },
    {
      "name": "Spur ±5 MHz",
      "state": "pass",
      "reason": "-70 dBc/side ≤-68 dBc/side; all-offset decision independent of integration bounds."
    },
    {
      "name": "Linear 2% first-and-stay",
      "state": "pass",
      "reason": "11.987174 µs ≤20.000000 µs; not nonlinear acquisition or wake time."
    }
  ],
  "verdict": "model-pass against illustrative criteria",
  "validMask": true,
  "random": {
    "area": 0.00020438886453479,
    "areaBy": {
      "reference": 0.00020429199371319032,
      "pfd": 2.0820102687267892e-8,
      "vco": 7.541826369661469e-8,
      "buffer": 6.324552158059099e-10
    },
    "phaseRad": 0.020218252374267665,
    "phaseDegrees": 1.1584205301758932,
    "timePs": 1.2618960023702541,
    "nodes": 4097
  },
  "combined": {
    "spurVariance": 0,
    "phaseRad": 0.020218252374267665,
    "timePs": 1.2618960023702541
  },
  "spurs": [
    {
      "id": "frac-10",
      "offset": 10000000,
      "dbc": -80,
      "name": "Fractional pair",
      "applicable": false,
      "inside": true,
      "selected": false,
      "included": false,
      "passes": true,
      "reason": "Fixture unavailable for this plan"
    },
    {
      "id": "frac-40",
      "offset": 40000000,
      "dbc": -65,
      "name": "Fractional / reference-PFD pair",
      "applicable": false,
      "inside": false,
      "selected": false,
      "included": false,
      "passes": false,
      "reason": "Fixture unavailable for this plan"
    },
    {
      "id": "int-5",
      "offset": 5000000,
      "dbc": -70,
      "name": "Exact-integer PFD pair",
      "applicable": true,
      "inside": true,
      "selected": false,
      "included": false,
      "passes": true,
      "reason": "Eligible for optional small-angle RMS"
    }
  ],
  "loop": {
    "ratio": 1.5427711592634117,
    "fn": 64818.427152698714,
    "wn": 407266.1891203269,
    "peaks": {
      "ref": {
        "f": 51071.99978186911,
        "power": 1.629304852807925
      },
      "vco": {
        "f": 458466.77032535936,
        "power": 1.0004001599327754
      },
      "nodes": 4097,
      "normalizedRange": "1e-4…1e4 × fn"
    }
  },
  "keyRows": [
    {
      "f": 10,
      "linear": {
        "reference": 0.00004064062693460979,
        "pfd": 6.9331115337010484e-12,
        "vco": 1.7914555898951567e-19,
        "buffer": 3.1622776601683796e-17
      },
      "total": 0.000040640633867753124,
      "dominant": "reference"
    },
    {
      "f": 100,
      "linear": {
        "reference": 4.064081846077413e-8,
        "pfd": 2.1924527041214863e-12,
        "vco": 1.791455758736266e-18,
        "buffer": 3.1622776601683796e-17
      },
      "total": 4.0643010946892486e-8,
      "dominant": "reference"
    },
    {
      "f": 1000,
      "linear": {
        "reference": 1.2857811156652989e-10,
        "pfd": 6.936411201141502e-13,
        "vco": 5.665133600090322e-17,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.2927184096075664e-10,
      "dominant": "reference"
    },
    {
      "f": 10000,
      "linear": {
        "reference": 4.255294891586212e-12,
        "pfd": 2.295606522023476e-13,
        "vco": 3.575802471627749e-15,
        "buffer": 3.1622776601683796e-17
      },
      "total": 4.48846296903679e-12,
      "dominant": "reference"
    },
    {
      "f": 100000,
      "linear": {
        "reference": 1.1081775959875382e-12,
        "pfd": 5.978292413856669e-14,
        "vco": 2.726773015886289e-13,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.4406694444913354e-12,
      "dominant": "reference"
    },
    {
      "f": 1000000,
      "linear": {
        "reference": 5.3162904820023855e-15,
        "pfd": 1.8095745958295941e-16,
        "vco": 1.0001504277636225e-14,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.5530374995823253e-14,
      "dominant": "vco"
    },
    {
      "f": 10000000,
      "linear": {
        "reference": 3.3467514868320887e-17,
        "pfd": 9.04880549087788e-19,
        "vco": 3.162282969028633e-16,
        "buffer": 3.1622776601683796e-17
      },
      "total": 3.8222346892195575e-16,
      "dominant": "vco"
    },
    {
      "f": 20000000,
      "linear": {
        "reference": 8.366733674693154e-18,
        "pfd": 2.262162156770701e-19,
        "vco": 1.5848938581680793e-16,
        "buffer": 3.1622776601683796e-17
      },
      "total": 1.9870511230886193e-16,
      "dominant": "vco"
    }
  ],
  "dominance": {
    "first": "reference",
    "boundaries": [
      {
        "from": "reference",
        "to": "vco",
        "lowerHz": 458313.1580395517,
        "upperHz": 459939.4518511602,
        "boundaryHz": 458432.98579893255
      }
    ]
  },
  "hardware": [
    "Evidence required: nominal 3.3 V supply; active synthesizer power ≤75 mW at actual operating conditions.",
    "Evidence required: sleep current ≤10 µA; define which reference and output buffers remain powered.",
    "Evidence required: wake request to spectrally usable LO ≤1.000 ms, including reference startup, nonlinear acquisition and spectral settling.",
    "Evidence required: 2.550000 GHz, +7.000 dBm delivered to the matched 50 Ω 04.6 mixer LO port; qualify buffer, loss, mismatch, pulling and drive at that plane.",
    "Evidence required: temperature, supply corners, real lock indication, output-load sensitivity, supply/control coupling and spurs in every operating mode."
  ],
  "meta": {
    "kernel": "p04-m07-pll-noise-v1",
    "allocator": "p04-m07-pll-allocator-v1",
    "decision": "p04-m07-decision-v1",
    "masks": "canonical-2p4-v1",
    "reference": "p04-m07-ref-mask-v1",
    "pfd": "p04-m07-pfd-mask-v1",
    "vco": "p04-m07-vco-mask-v1",
    "spurs": "p04-m07-paired-spurs-v1",
    "evidence": "Illustrative / Simulated; never measured",
    "convention": "e^(+jωt); positive-offset one-sided SSB L in dBc/Hz, normalized to 1 Hz; Sφ,one-sided=2Llinear; Sφ,two-sided=Llinear",
    "plane": "Final ideal divided output, before any real LO-load interface",
    "validity": "Exactly 40 MHz original reference; nominal VCO and final output 2.35–2.55 GHz; nominal PFD 5–40 MHz; inclusive exact-rational comparisons. Tolerance corners do not move nominal lookup.",
    "interpolation": "dB linear versus log10(offset), 10 Hz–20 MHz, no extrapolation; flat across the valid nominal carrier range",
    "integration": "4097 log nodes: 10×2000000^(i/4096) Hz; forced endpoints; inserted exact bounds once, interior nodes retained; ordinary-Hz trapezoids; 8193-node independent convergence <2e-5 relative",
    "loop": "Normalized continuous second-order type-II, fc is open-loop unity-gain crossover; no sampled-data or physical loop-filter synthesis",
    "settling": "65537 uniform samples to 20/pslow; final entering 2% crossing linearly interpolated; monotone tail bound <0.02 required",
    "dominance": "4097 full-span nodes; relative ties ≤1e-12 prefer reference, PFD proxy, VCO, buffer; changed-winner dB zero interpolated versus log offset",
    "precision": "Internals unrounded; displays half away from zero: MHz/GHz/dB/µs 6 decimals, ps 5 decimals",
    "source": "Local frozen builder tables, independent Python oracle; theory: Banerjee 5th ed. SNAA106C (2017), ADI MT-008 Rev. A (2008)"
  },
  "settling": {
    "timeUs": 11.987174464897043,
    "horizon": 0.00007015418744468164,
    "tail": 2.886192367622901e-9,
    "crossings": [
      0.0000026307966859668614,
      0.000011987174464897043
    ],
    "samples": 65537,
    "dominantUs": 13.722239760535647,
    "envelopeUs": 14.903188260648689,
    "trace": [
      {
        "t": 0,
        "error": 1
      },
      {
        "t": 0.000008769273430585204,
        "error": -0.11299510413558037
      },
      {
        "t": 0.00001753854686117041,
        "error": 0.00866515868896817
      },
      {
        "t": 0.000026307820291755613,
        "error": -0.00041984973919866763
      },
      {
        "t": 0.00003507709372234082,
        "error": -0.000001152901149219045
      },
      {
        "t": 0.00004384636715292602,
        "error": 0.000002986084827301228
      },
      {
        "t": 0.00005261564058351123,
        "error": -3.9928467213503486e-7
      },
      {
        "t": 0.00006138491401409643,
        "error": 3.430903800952969e-8
      },
      {
        "t": 0.00007015418744468164,
        "error": -1.986531625132905e-9
      }
    ]
  },
  "hardwareRequest": {
    "supplyV": 3.3,
    "activePowerMaxMw": 75,
    "sleepCurrentMaxUa": 10,
    "wakeMaxMs": 1,
    "loHz": 2550000000,
    "deliveredDbm": 7,
    "loadOhm": 50,
    "temperature": "25 °C illustrative nominal; hardware temperature corners evidence required",
    "sourceStatus": "2026-09-06; synthetic masks, no device fit"
  },
  "verification": "Request condition-matched reference/PFD/VCO/buffer noise, per-side spurs at all relevant offsets, LO drive under real load, frequency corners, nonlinear wake and supply/current measurements."
}

Gateway front-end component review

Ungraded, printable Path 04 capstone. Build one conditional evidence pack from all seven modules. The worked fixtures remain separate experiments until compatible ports, bandwidths, stimulus statistics and operating conditions support a cascade. No score, submission, saved progress or certificate is created here.

Capstone input brief · illustrative node and gateway; preserve variants, not an implied simulated system
Input / plane	Supplied condition and evidence boundary
Wanted waveform	Portfolio normal mode: 2.450 GHz QPSK, 20 kbit/s information, 10 ksymbol/s, RRC α=0.35, 256-symbol burst. The PA uses its separate frozen normalized sample record; do not assign that record a new rate.
Gateway observation variant from 04.6	RF support 2.400–2.500 GHz, −80 dBm total available at R1-RF; 100 MHz IF center. This full-band screening input is not the narrow telemetry waveform.
Threats from earlier modules	04.3: −20 dBm at 2.750 GHz; 04.4: −25 dBm input CW blocker; 04.6: low-side image 2.250 GHz, −30 dBm tone, plus 2.390 GHz clock. Keep each source’s plane and stimulus distinct; retain the complete 04.6 spur table.
Antenna / network boundary	R2 external antenna interface, nominal real 50 Ω; PA fixture Γ at R1-out corresponds to VSWR 2 ∠0°. Transform real R2 reflections through the network before using them at R1. Local RF/LO/IF and coupled-port names must be attached.
Supply / temperature	Synthesizer request: nominal 3.3 V, ≤75 mW active, ≤10 µA sleep, ≤1 ms spectrally usable wake. Earlier block biases remain per card. Review −40…+85 °C as an illustrative hardware envelope, already used in 04.1; most analytic block fixtures are only nominal 25 °C and do not qualify those corners.
Mixer / synthesizer interface	High-side 2.550 GHz LO candidate, +7 dBm matched LO plane. Frequency and noise evidence at ideal divider output does not prove the real loaded interface.

Receive / observeR2 antenna → switch/protection → preselector → R1 LNA input/output → R1-RF mixer → A1-IF filter/receiver. Synthesizer divided output → qualified buffer/network → R1-LO mixer. A sampled PA path can instead enter from the declared coupler P3 observation port.
Transmit / sampleR1 PA input → PA → R1-out → coupler P1/P2 → switch → R2 antenna. Coupler P3 → observation receiver; isolated P4 → explicitly rated 50 Ω termination. Specify off-state branch loads.

Candidate model excerpts to carry forward · original evidence labels and conditions travel with every value
Module / candidate	Conditional excerpt	Unresolved risk / requested discriminator
04.1 model card	Package R1, e^(+jωt), frequency, voltage/bias, drive, temperature, model revision and interpolation declared	Reject typical-as-guaranteed and out-of-domain S-parameter use; compare at compatible planes.
04.2 routing / coupling	Terminated multiport state with named common/through/coupled/isolated ports; passive powers in watts	Directivity/mismatch ambiguity, off-state loading, power ratings, protection/recovery and PIM evidence.
04.3 filter candidate	Butterworth n=4, common Aedge=0.4 dB, Q proxy=500; 2.4–2.5 GHz passband, ≥40 dB at 2.75 GHz	Physical realization, complex match, loss/delay corners and other image/harmonic regions; no physical circuit inferred from prototype.
04.4 nominal matched LNA	2.450 GHz, 25 °C, 3 V/15 mA proxy; GT=13.064250 dB, NF=1.272028 dB; 15 dB CW blocker margin	Termination/bias-wide stability, nonlinear blocking and corner evidence. The separate 1.5 dB matched pre-loss must be reconciled with the selected filter.
04.5 PA node baseline	+10 dBm requested linear-output QPSK; 9.996939 dBm actual forward average; 88.207479 µJ per frozen cycle; R1-out VSWR 2 ∠0°	Memory, thermal state, spectrum, real burst recovery and all-phase ruggedness; forward is not accepted antenna power.
04.6 high-side mixer candidate	2.550 GHz LO, +7 dBm, 7 dB fundamental conversion proxy, 25 °C matched 50 Ω; 100 MHz IF	Higher-order product amplitudes unknown; preselection, isolation and load-qualified conversion evidence still required.
04.7 selected synthesizer	R=8, N=510, D=1; PFD=5 MHz, fc=100 kHz, ζ=0.70; 2.550 GHz, zero programmed error; synthetic 1.26190 ps random jitter	Attach complete mask/plane/bound/criterion record. +7 dBm, startup/nonlinear acquisition, supply, sleep and temperature remain evidence required.

Your review must draw one selected chain, attach a conditional model card for every selected block, allocate gain/noise/linearity/power/spur/phase-noise risks, and reject at least two alternatives with causal reasons. Include the full synthesizer record, missing operating-condition evidence and a discriminating vendor-data or measurement request that could overturn each choice. Label what is Derived, Simulated, Illustrative, Measured or still unknown; none of these synthetic curves is Measured.

Transparent self-review rubric · no grading or pass/fail implementation
Review dimension	Weight	Question to ask your evidence pack
Model validity	20%	Are domain, stimulus, bias, temperature, revision, plane and limitations intact?
Network / block correctness	25%	Do ports, direction, terminations, frequency translation, noise mapping and power ratios agree?
Waveform / system consequences	20%	Are wanted content, blockers, distortion, phase noise and spurs connected to specific consequences?
Operating-condition / stability risk	20%	Are mismatch, supply, temperature, startup and nonlinear states supported or explicitly unknown?
Traceable evidence	15%	Can another engineer reproduce the arithmetic, inspect the source and identify a falsifying check?

A defensible review cannot use a typical parameter as a guaranteed limit or apply an S-parameter claim outside its bias/power domain. All seven Path 04 lessons now contribute to this component review. Continue with From Product Need to RF Requirements to connect these conditional blocks to owned system requirements. The remaining Path 05 architecture and budget lessons are planned.

Ungraded review

Check your understanding

Answer each question in your own words, then reveal the model answer.

01Why do N=61.25/R=1 and N=490/R=8 have the same original-reference noise multiplication at D=1?
Model answer
Both give N/R=61.25, so 20log₁₀[N/(RD)]=35.742122 dB. The 53.803922 dB 20log490 value applies to a mask already at the PFD comparison input. D must be included for final-output scaling.
02Can a 40 MHz PFD with integer N produce 2.450 GHz and represent a 10 MHz channel step at D=1?
Model answer
No. Nearest integer output is 2.440 GHz at N=61, error −10 MHz; N=62 gives 2.480 GHz. The integer quantum is 40 MHz, so 10 MHz is one quarter of a quantum. R=8 gives 5 MHz PFD and exact N=490; fractional 61+1024/4096 is also exact at R=1.
03How does a one-sided SSB density become time jitter, and where does a −80 dBc/side pair go?
Model answer
Convert each mapped dBc/Hz value to linear density, sum, integrate in Hz between explicit bounds, then σφ=sqrt(2×area) and σt=σφ/(2πfactual). Keep random-only visible. An explicitly selected applicable in-bound symmetric pair adds 2×10⁻⁸ rad², not a density trapezoid.
04What do Href and Hvco do at DC and high offset? Is fc the natural frequency?
Model answer
At DC Href=1 and Hvco=0; at high offset they approach 0 and 1. They sum as complex amplitudes to one, not generally in squared magnitude. fc is open-loop unity-gain crossover; at ζ=.70, fc/fn=1.542771159, so 100 kHz means fn=64.818427 kHz.
05Why does the fractional default reject despite 1.26185 ps random jitter, and can narrowing the integration bounds remove that rejection?
Model answer
The applicable −65 dBc/side pair at ±40 MHz exceeds the −68 dBc/side limit. All-offset spur limits are independent of the 10 Hz–20 MHz random integration. The 40 MHz pair is excluded from optional bounded RMS but remains in the discrete decision.
06What does the 2.550 GHz integer model-pass leave unproven?
Model answer
It supports only the local exact plan, valid synthetic masks, random jitter, spur fixtures and linear settling criteria. It does not prove +7 dBm delivered LO drive, pulling, real lock, reference startup, nonlinear acquisition, ≤1 ms spectral wake, ≤75 mW active power, ≤10 µA sleep, supply/temperature corners or modulation quality. Keep the separate hardware-inspect record.

Sources and further study

Primary-source access checked 6 September 2026. All plotted data are independently checked local analytic fixtures (p04-m07-pll-noise-v1), not digitized vendor curves. Web-only articles have no verified revision identifier. Hardware examples keep their own conditions and do not qualify the recurring case.

Ian Collins, Phase-Locked Loop (PLL) Fundamentals, Analog Devices, CIR-3; current official article. Block roles, injection-side tradeoffs and fractional architecture orientation.
How to Design and Debug a Phase-Locked Loop Circuit, Analog Devices, CIR-3; current official article. Control and observation-node context; no measurement procedure reproduced.
Dean Banerjee, PLL Performance, Simulation, and Design, fifth edition, Texas Instruments SNAA106C, May 2017. Chapters 4, 12, 22, 26, 28 and 46: oscillator/control/noise conventions, integration, transients and lock observation. The lesson retains its specified numerator zero and derives its own exact branches.
Walt Kester, MT-008: Converting Oscillator Phase Noise to Time Jitter, Analog Devices, Rev. A, October 2008. SSB and small-angle jitter mapping; masks and bounds here are local.
Rohde & Schwarz, Understanding EVM, 3683.8038.52, version 01.00, October 2022 (SYS-3). Waveform-quality interpretation only; no standard limit or EVM prediction adopted.
Analog Devices ADF4351, data sheet Rev. A; current official PDF. Table 1 footnote 6 and Figure 10 condition audit; its device limits do not define this allocator.
Analog Devices HMC385LP4 / LP4E, v02.0705; current official PDF. Free-running RF-output phase-noise, load pulling and supply pushing conditions.
SiTime SiT8208, Rev. 1.02, 24 June 2013; current official PDF endpoint. Reference stability, loaded logic-output jitter, standby and startup/resume distinctions.
Keysight E5055A, Spurious Measurement, current online help, no visible pinned revision. Discrete-spur reporting and omission vocabulary; procedures deferred to Path 08.

Oscillators &Phase-Locked Loops

Failure: the carrier is correct, the waveform fails

How oscillation is sustained

Accuracy, drift, aging, pulling, and pushing

Phase noise and bounded jitter

Inside the PLL loop

Divider ratio, PFD rate, and integer-N channel grid

Fractional-N flexibility and fractional artifacts

Loop bandwidth trades noise against settling

Spurs, supply coupling, layout, and lock detection

Allocate the node and gateway synthesizer

Gateway front-end component review

Check your understanding

Sources and further study

Oscillators &
Phase-Locked Loops